projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 47d41cc3 | 1 | /* |
| 21608275 | 2 | * Copyright 2009-2010 Freescale Semiconductor, Inc. |
| 47d41cc3 KG |
3 | * |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License as | |
| 6 | * published by the Free Software Foundation; either version 2 of | |
| 7 | * the License, or (at your option) any later version. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License | |
| 15 | * along with this program; if not, write to the Free Software | |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 17 | * MA 02111-1307 USA | |
| 18 | * | |
| 19 | */ | |
| 20 | ||
| 21 | #ifndef _ASM_CONFIG_H_ | |
| 22 | #define _ASM_CONFIG_H_ | |
| 23 | ||
| a16028da | 24 | #define CONFIG_LMB |
| fca43cc8 JR |
25 | #define CONFIG_SYS_BOOT_RAMDISK_HIGH |
| 26 | #define CONFIG_SYS_BOOT_GET_CMDLINE | |
| 27 | #define CONFIG_SYS_BOOT_GET_KBD | |
| a16028da | 28 | |
| 87c90639 | 29 | #ifndef CONFIG_MAX_MEM_MAPPED |
| bd76729b | 30 | #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
| 87c90639 KG |
31 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) |
| 32 | #else | |
| 2ede879f | 33 | #define CONFIG_MAX_MEM_MAPPED (256 << 20) |
| 87c90639 KG |
34 | #endif |
| 35 | #endif | |
| 36 | ||
| f732a759 PT |
37 | /* Check if boards need to enable FSL DMA engine for SDRAM init */ |
| 38 | #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) | |
| 39 | #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ | |
| 40 | ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ | |
| 41 | !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) | |
| 017f11f6 | 42 | #define CONFIG_FSL_DMA |
| 47d41cc3 | 43 | #endif |
| 017f11f6 PT |
44 | #endif |
| 45 | ||
| 3b1f243b | 46 | #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ |
| 21608275 | 47 | defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ |
| 3b1f243b | 48 | defined(CONFIG_P2020) || defined(CONFIG_MPC8641) |
| 7e4259bb | 49 | #define CONFIG_MAX_CPUS 2 |
| c26de2d8 KG |
50 | #elif defined(CONFIG_PPC_P3041) |
| 51 | #define CONFIG_MAX_CPUS 4 | |
| 7e4259bb KG |
52 | #elif defined(CONFIG_PPC_P4080) |
| 53 | #define CONFIG_MAX_CPUS 8 | |
| 19dbcc96 KG |
54 | #elif defined(CONFIG_PPC_P5020) |
| 55 | #define CONFIG_MAX_CPUS 2 | |
| 0e870980 | 56 | #else |
| 7e4259bb | 57 | #define CONFIG_MAX_CPUS 1 |
| 0e870980 PA |
58 | #endif |
| 59 | ||
| 5ccd29c3 PT |
60 | /* |
| 61 | * Provide a default boot page translation virtual address that lines up with | |
| 62 | * Freescale's default e500 reset page. | |
| 63 | */ | |
| 64 | #if (defined(CONFIG_E500) && defined(CONFIG_MP)) | |
| 65 | #ifndef CONFIG_BPTR_VIRT_ADDR | |
| 66 | #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 | |
| 67 | #endif | |
| 68 | #endif | |
| 69 | ||
| 3ad89c4e KG |
70 | /* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ |
| 71 | #if defined(CONFIG_TSEC_ENET) && \ | |
| 72 | (defined(CONFIG_P1020) || defined(CONFIG_P1011)) | |
| 73 | #define CONFIG_TSECV2 | |
| 74 | #endif | |
| 75 | ||
| 929a2138 KP |
76 | /* |
| 77 | * SEC (crypto unit) major compatible version determination | |
| 78 | */ | |
| 22f292c7 KP |
79 | #if defined(CONFIG_FSL_CORENET) |
| 80 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 81 | #elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) | |
| 929a2138 KP |
82 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 83 | #endif | |
| 84 | ||
| 94e9411b KG |
85 | /* Number of TLB CAM entries we have on FSL Book-E chips */ |
| 86 | #if defined(CONFIG_E500MC) | |
| 87 | #define CONFIG_SYS_NUM_TLBCAMS 64 | |
| 88 | #elif defined(CONFIG_E500) | |
| 89 | #define CONFIG_SYS_NUM_TLBCAMS 16 | |
| 90 | #endif | |
| 91 | ||
| 85829017 PT |
92 | /* Relocation to SDRAM works on all PPC boards */ |
| 93 | #define CONFIG_RELOC_FIXUP_WORKS | |
| 94 | ||
| f51cdaf1 BB |
95 | /* Since so many PPC SOCs have a semi-common LBC, define this here */ |
| 96 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ | |
| 97 | defined(CONFIG_MPC83xx) | |
| 98 | #define CONFIG_FSL_LBC | |
| 99 | #endif | |
| 100 | ||
| f2a37fcd AA |
101 | /* All PPC boards must swap IDE bytes */ |
| 102 | #define CONFIG_IDE_SWAP_IO | |
| 103 | ||
| 017f11f6 | 104 | #endif /* _ASM_CONFIG_H_ */ |