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243be8e2 | 1 | /* |
19a8dbdc | 2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. |
243be8e2 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
243be8e2 KG |
5 | */ |
6 | ||
7 | #ifndef _ASM_MPC85xx_CONFIG_H_ | |
8 | #define _ASM_MPC85xx_CONFIG_H_ | |
9 | ||
10 | /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ | |
11 | ||
e46fedfe TT |
12 | #ifdef CONFIG_SYS_CCSRBAR_DEFAULT |
13 | #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." | |
14 | #endif | |
15 | ||
2a5fcb83 YS |
16 | /* |
17 | * This macro should be removed when we no longer care about backwards | |
18 | * compatibility with older operating systems. | |
19 | */ | |
20 | #define CONFIG_PPC_SPINTABLE_COMPATIBLE | |
21 | ||
34e026f9 YS |
22 | #include <fsl_ddrc_version.h> |
23 | #define CONFIG_SYS_FSL_DDR_BE | |
57495e4e | 24 | |
1b4175d6 PK |
25 | /* IP endianness */ |
26 | #define CONFIG_SYS_FSL_IFC_BE | |
028dbb8d | 27 | #define CONFIG_SYS_FSL_SEC_BE |
1b4175d6 | 28 | |
243be8e2 KG |
29 | /* Number of TLB CAM entries we have on FSL Book-E chips */ |
30 | #if defined(CONFIG_E500MC) | |
31 | #define CONFIG_SYS_NUM_TLBCAMS 64 | |
32 | #elif defined(CONFIG_E500) | |
33 | #define CONFIG_SYS_NUM_TLBCAMS 16 | |
34 | #endif | |
35 | ||
36 | #if defined(CONFIG_MPC8536) | |
37 | #define CONFIG_MAX_CPUS 1 | |
38 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
e4879afb | 39 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 |
243be8e2 | 40 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 41 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
9855b3be | 42 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 43 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 44 | |
d1a24f06 | 45 | #elif defined(CONFIG_MPC8540) |
243be8e2 KG |
46 | #define CONFIG_MAX_CPUS 1 |
47 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 48 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
e46fedfe | 49 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 | 50 | |
d1a24f06 | 51 | #elif defined(CONFIG_MPC8541) |
243be8e2 KG |
52 | #define CONFIG_MAX_CPUS 1 |
53 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 54 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
243be8e2 | 55 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 56 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
57 | |
58 | #elif defined(CONFIG_MPC8544) | |
59 | #define CONFIG_MAX_CPUS 1 | |
60 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 61 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
e4879afb | 62 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 |
243be8e2 | 63 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 64 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
954a1a47 | 65 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
66 | |
67 | #elif defined(CONFIG_MPC8548) | |
68 | #define CONFIG_MAX_CPUS 1 | |
69 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 70 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
e4879afb | 71 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 |
243be8e2 | 72 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 73 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
5ace2992 | 74 | #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 |
2b3a1cdd | 75 | #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 |
aada81de | 76 | #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
7d67ed58 LG |
77 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
78 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
79 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
80 | #define CONFIG_SYS_FSL_RMU | |
81 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
954a1a47 | 82 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
83 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
84 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 | |
243be8e2 KG |
85 | |
86 | #elif defined(CONFIG_MPC8555) | |
87 | #define CONFIG_MAX_CPUS 1 | |
88 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 89 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
243be8e2 | 90 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 91 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
92 | |
93 | #elif defined(CONFIG_MPC8560) | |
94 | #define CONFIG_MAX_CPUS 1 | |
95 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 96 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
e46fedfe | 97 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
98 | |
99 | #elif defined(CONFIG_MPC8568) | |
100 | #define CONFIG_MAX_CPUS 1 | |
101 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 102 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
243be8e2 | 103 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
fdb4dad3 KG |
104 | #define QE_MURAM_SIZE 0x10000UL |
105 | #define MAX_QE_RISC 2 | |
106 | #define QE_NUM_OF_SNUM 28 | |
e46fedfe | 107 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
7d67ed58 LG |
108 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
109 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
110 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
111 | #define CONFIG_SYS_FSL_RMU | |
112 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
243be8e2 KG |
113 | |
114 | #elif defined(CONFIG_MPC8569) | |
115 | #define CONFIG_MAX_CPUS 1 | |
116 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
117 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
fdb4dad3 KG |
118 | #define QE_MURAM_SIZE 0x20000UL |
119 | #define MAX_QE_RISC 4 | |
120 | #define QE_NUM_OF_SNUM 46 | |
e46fedfe | 121 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
7d67ed58 LG |
122 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
123 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
124 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
125 | #define CONFIG_SYS_FSL_RMU | |
126 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
9855b3be | 127 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 128 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
129 | |
130 | #elif defined(CONFIG_MPC8572) | |
131 | #define CONFIG_MAX_CPUS 2 | |
132 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
e4879afb | 133 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 134 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 135 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
eb0aff77 | 136 | #define CONFIG_SYS_FSL_ERRATUM_DDR_115 |
91671913 | 137 | #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 |
9855b3be | 138 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 139 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
140 | |
141 | #elif defined(CONFIG_P1010) | |
142 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 143 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 144 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
ad75d442 | 145 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 |
243be8e2 KG |
146 | #define CONFIG_TSECV2 |
147 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
148 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
149 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 150 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
362ee04b | 151 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 |
1fbf3483 | 152 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
8f29084a | 153 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
1b719e66 | 154 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 155 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 156 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
424bf942 | 157 | #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 |
bc6bbd6b | 158 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
954a1a47 | 159 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb | 160 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9855b3be | 161 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
11856919 | 162 | #define CONFIG_SYS_FSL_ERRATUM_A007075 |
9c641a87 | 163 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 164 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 |
f28bea00 | 165 | #define CONFIG_ESDHC_HC_BLK_ADDR |
243be8e2 | 166 | |
093cffbe | 167 | /* P1011 is single core version of P1020 */ |
243be8e2 KG |
168 | #elif defined(CONFIG_P1011) |
169 | #define CONFIG_MAX_CPUS 1 | |
170 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 171 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 172 | #define CONFIG_TSECV2 |
b03a466d | 173 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 174 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
f1810d85 | 175 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 176 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
177 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
178 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
9855b3be | 179 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 180 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 181 | |
093cffbe | 182 | /* P1012 is single core version of P1021 */ |
243be8e2 KG |
183 | #elif defined(CONFIG_P1012) |
184 | #define CONFIG_MAX_CPUS 1 | |
185 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
f1810d85 | 186 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ad75d442 | 187 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 188 | #define CONFIG_TSECV2 |
b03a466d | 189 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 190 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 191 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
192 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
193 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
194 | #define QE_MURAM_SIZE 0x6000UL |
195 | #define MAX_QE_RISC 1 | |
196 | #define QE_NUM_OF_SNUM 28 | |
9855b3be | 197 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 198 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 199 | |
093cffbe | 200 | /* P1013 is single core version of P1022 */ |
243be8e2 KG |
201 | #elif defined(CONFIG_P1013) |
202 | #define CONFIG_MAX_CPUS 1 | |
203 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
f1810d85 | 204 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ad75d442 | 205 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 KG |
206 | #define CONFIG_TSECV2 |
207 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 208 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
209 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
210 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
211 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
9855b3be | 212 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 213 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
214 | |
215 | #elif defined(CONFIG_P1014) | |
216 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 217 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 218 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
ad75d442 | 219 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 |
243be8e2 KG |
220 | #define CONFIG_TSECV2 |
221 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
222 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
223 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 224 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
1fbf3483 | 225 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
1b719e66 | 226 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 227 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 228 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
bc6bbd6b | 229 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
9855b3be | 230 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
243be8e2 | 231 | |
093cffbe | 232 | /* P1017 is single core version of P1023 */ |
67a719da RZ |
233 | #elif defined(CONFIG_P1017) |
234 | #define CONFIG_MAX_CPUS 1 | |
235 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
236 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
237 | #define CONFIG_SYS_NUM_FMAN 1 | |
238 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
239 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 240 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
67a719da RZ |
241 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 |
242 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 243 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 244 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 245 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
9855b3be | 246 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 247 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
67a719da | 248 | |
243be8e2 KG |
249 | #elif defined(CONFIG_P1020) |
250 | #define CONFIG_MAX_CPUS 2 | |
251 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 252 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 253 | #define CONFIG_TSECV2 |
b03a466d | 254 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 255 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 256 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
257 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
258 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
9855b3be | 259 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 260 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
80ba6a6f | 261 | #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT |
f1810d85 | 262 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
80ba6a6f | 263 | #endif |
243be8e2 KG |
264 | |
265 | #elif defined(CONFIG_P1021) | |
266 | #define CONFIG_MAX_CPUS 2 | |
267 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 268 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 269 | #define CONFIG_TSECV2 |
b03a466d | 270 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 271 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 272 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
273 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
274 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
275 | #define QE_MURAM_SIZE 0x6000UL |
276 | #define MAX_QE_RISC 1 | |
277 | #define QE_NUM_OF_SNUM 28 | |
9855b3be | 278 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 279 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1810d85 | 280 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
243be8e2 KG |
281 | |
282 | #elif defined(CONFIG_P1022) | |
283 | #define CONFIG_MAX_CPUS 2 | |
284 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 285 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 KG |
286 | #define CONFIG_TSECV2 |
287 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
f1810d85 | 288 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 289 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
290 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
291 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
292 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
9855b3be | 293 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 294 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 295 | |
67a719da RZ |
296 | #elif defined(CONFIG_P1023) |
297 | #define CONFIG_MAX_CPUS 2 | |
298 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
299 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
300 | #define CONFIG_SYS_NUM_FMAN 1 | |
301 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
302 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 303 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
67a719da RZ |
304 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 |
305 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 306 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 307 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 308 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
9855b3be | 309 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 310 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
311 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
312 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
67a719da | 313 | |
093cffbe KG |
314 | /* P1024 is lower end variant of P1020 */ |
315 | #elif defined(CONFIG_P1024) | |
316 | #define CONFIG_MAX_CPUS 2 | |
317 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 318 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
093cffbe KG |
319 | #define CONFIG_TSECV2 |
320 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
321 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
f1810d85 | 322 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 323 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
324 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
325 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
9855b3be | 326 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 327 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
093cffbe KG |
328 | |
329 | /* P1025 is lower end variant of P1021 */ | |
330 | #elif defined(CONFIG_P1025) | |
331 | #define CONFIG_MAX_CPUS 2 | |
332 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
f1810d85 | 333 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ad75d442 | 334 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
093cffbe KG |
335 | #define CONFIG_TSECV2 |
336 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
337 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 338 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
339 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
340 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
341 | #define QE_MURAM_SIZE 0x6000UL |
342 | #define MAX_QE_RISC 1 | |
343 | #define QE_NUM_OF_SNUM 28 | |
9855b3be | 344 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 345 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
093cffbe KG |
346 | |
347 | /* P2010 is single core version of P2020 */ | |
243be8e2 KG |
348 | #elif defined(CONFIG_P2010) |
349 | #define CONFIG_MAX_CPUS 1 | |
350 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 351 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 352 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
f1810d85 | 353 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
e46fedfe | 354 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 355 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 356 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
9855b3be | 357 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 358 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
359 | |
360 | #elif defined(CONFIG_P2020) | |
361 | #define CONFIG_MAX_CPUS 2 | |
362 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 363 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 364 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 365 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 366 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 367 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
7d67ed58 LG |
368 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
369 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
370 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
371 | #define CONFIG_SYS_FSL_RMU | |
372 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
9855b3be | 373 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 374 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1810d85 | 375 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
9855b3be | 376 | |
3e978f5d | 377 | #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ |
d1001e3f | 378 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 379 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
1f97987a KG |
380 | #define CONFIG_MAX_CPUS 4 |
381 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
382 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
383 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
384 | #define CONFIG_SYS_NUM_FMAN 1 | |
385 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
386 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
387 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 388 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
1f97987a KG |
389 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
390 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 | |
391 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
e46fedfe | 392 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
1f97987a KG |
393 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
394 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 395 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
1f97987a | 396 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5e23ab0a | 397 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
99d7b0a4 | 398 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
43f082bb | 399 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
e22be77a | 400 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 401 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
402 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
403 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
404 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
405 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
406 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
407 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
408 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 409 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 410 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
9c3f77eb | 411 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 412 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 413 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 |
1f97987a | 414 | |
243be8e2 | 415 | #elif defined(CONFIG_PPC_P3041) |
d1001e3f | 416 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 417 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 418 | #define CONFIG_MAX_CPUS 4 |
b5c8753f | 419 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
420 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
421 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
422 | #define CONFIG_SYS_NUM_FMAN 1 |
423 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
424 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
425 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
34e026f9 | 426 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 |
c657d898 | 427 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 428 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 429 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 430 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
431 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
432 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 433 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
f1810d85 | 434 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
30009766 | 435 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
57125f22 | 436 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
99d7b0a4 | 437 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
43f082bb | 438 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
e22be77a | 439 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 440 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
441 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
442 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
443 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
444 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
445 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
446 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
447 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 448 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 449 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
d217a9ad | 450 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
9c3f77eb | 451 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 452 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 453 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 454 | |
3e978f5d | 455 | #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ |
d1001e3f | 456 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 457 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 458 | #define CONFIG_MAX_CPUS 8 |
b5c8753f | 459 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
243be8e2 KG |
460 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
461 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
462 | #define CONFIG_SYS_NUM_FMAN 2 | |
463 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
464 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 | |
465 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
466 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
467 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 468 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 469 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
c657d898 | 470 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 471 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
8f29084a | 472 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" |
e46fedfe | 473 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
243be8e2 KG |
474 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
475 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 | |
fa8d23c0 | 476 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
243be8e2 KG |
477 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
478 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
479 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
4e0be34a | 480 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 |
243be8e2 | 481 | #define CONFIG_SYS_P4080_ERRATUM_CPU22 |
5e23ab0a | 482 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
243be8e2 | 483 | #define CONFIG_SYS_P4080_ERRATUM_SERDES8 |
df8af0b4 | 484 | #define CONFIG_SYS_P4080_ERRATUM_SERDES9 |
d90fdba6 | 485 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
da30b9fd | 486 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 |
43f082bb | 487 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
4108508a | 488 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
489 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
490 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
491 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
492 | #define CONFIG_SYS_FSL_RMU | |
493 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
33eee330 SW |
494 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
495 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 | |
496 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 | |
d59c5570 | 497 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 498 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
d607b968 | 499 | #define CONFIG_SYS_FSL_ERRATUM_A004580 |
c0a4e6b8 | 500 | #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 |
d217a9ad | 501 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
9c3f77eb | 502 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
11856919 | 503 | #define CONFIG_SYS_FSL_ERRATUM_A007075 |
9c3f77eb | 504 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 505 | |
3e978f5d | 506 | #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ |
ffd06e02 | 507 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
d1001e3f | 508 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 509 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 510 | #define CONFIG_MAX_CPUS 2 |
b5c8753f | 511 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
512 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
513 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
514 | #define CONFIG_SYS_NUM_FMAN 1 |
515 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
516 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
517 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 518 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 519 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
c657d898 | 520 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 521 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 522 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 523 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
524 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
525 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 526 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
30009766 | 527 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
99d7b0a4 | 528 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
e22be77a | 529 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 530 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
531 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
532 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
533 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
534 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
535 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
536 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 | |
d59c5570 | 537 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
9c3f77eb | 538 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 539 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 540 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 541 | |
4905443f | 542 | #elif defined(CONFIG_PPC_P5040) |
1956e431 | 543 | #define CONFIG_SYS_PPC64 |
4905443f | 544 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 545 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
4905443f TT |
546 | #define CONFIG_MAX_CPUS 4 |
547 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 | |
548 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
549 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
550 | #define CONFIG_SYS_NUM_FMAN 2 | |
551 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
552 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
553 | #define CONFIG_SYS_NUM_FM2_DTSEC 5 | |
554 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
555 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 556 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 557 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
4905443f TT |
558 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
559 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
560 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
561 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
562 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
563 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
564 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
565 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
99d7b0a4 | 566 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
4905443f TT |
567 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
568 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 | |
569 | #define CONFIG_SYS_FSL_ERRATUM_A004699 | |
4905443f TT |
570 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
571 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
9c641a87 | 572 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
4905443f | 573 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 |
d217a9ad | 574 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
4905443f | 575 | |
19a8dbdc PK |
576 | #elif defined(CONFIG_BSC9131) |
577 | #define CONFIG_MAX_CPUS 1 | |
578 | #define CONFIG_FSL_SDHC_V2_3 | |
579 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
580 | #define CONFIG_TSECV2 | |
581 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
582 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
34e026f9 | 583 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 584 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
765b0bdb PJ |
585 | #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 |
586 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 | |
362ee04b | 587 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 |
19a8dbdc PK |
588 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
589 | #define CONFIG_NAND_FSL_IFC | |
19a8dbdc | 590 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
954a1a47 | 591 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f28bea00 | 592 | #define CONFIG_ESDHC_HC_BLK_ADDR |
19a8dbdc | 593 | |
35fe948e PK |
594 | #elif defined(CONFIG_BSC9132) |
595 | #define CONFIG_MAX_CPUS 2 | |
596 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 | |
597 | #define CONFIG_FSL_SDHC_V2_3 | |
598 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
599 | #define CONFIG_TSECV2 | |
600 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
601 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 602 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 |
f1810d85 | 603 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
64501c66 PJ |
604 | #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 |
605 | #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 | |
606 | #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 | |
607 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 | |
061ffeda | 608 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 |
35fe948e PK |
609 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
610 | #define CONFIG_NAND_FSL_IFC | |
35fe948e PK |
611 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
612 | #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK | |
613 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
954a1a47 | 614 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1a96ec1 | 615 | #define CONFIG_SYS_FSL_ERRATUM_A005434 |
9c3f77eb CL |
616 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
617 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
f28bea00 | 618 | #define CONFIG_ESDHC_HC_BLK_ADDR |
35fe948e | 619 | |
5122dfae SL |
620 | #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ |
621 | defined(CONFIG_PPC_T4080) | |
3d2972fe | 622 | #define CONFIG_E6500 |
ffd06e02 | 623 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
9e758758 YS |
624 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
625 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
f6981439 | 626 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |
9e758758 | 627 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ |
3d2972fe | 628 | #ifdef CONFIG_PPC_T4240 |
9e758758 | 629 | #define CONFIG_MAX_CPUS 12 |
ce746fe0 | 630 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } |
9e758758 YS |
631 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 |
632 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
633 | #define CONFIG_SYS_NUM_FM2_DTSEC 8 | |
634 | #define CONFIG_SYS_NUM_FM2_10GEC 2 | |
635 | #define CONFIG_NUM_DDR_CONTROLLERS 3 | |
3d2972fe | 636 | #else |
5122dfae | 637 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 |
3d2972fe | 638 | #define CONFIG_SYS_NUM_FM1_10GEC 1 |
5122dfae | 639 | #define CONFIG_SYS_NUM_FM2_DTSEC 8 |
3d2972fe YS |
640 | #define CONFIG_SYS_NUM_FM2_10GEC 1 |
641 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
5122dfae SL |
642 | #if defined(CONFIG_PPC_T4160) |
643 | #define CONFIG_MAX_CPUS 8 | |
644 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } | |
645 | #elif defined(CONFIG_PPC_T4080) | |
646 | #define CONFIG_MAX_CPUS 4 | |
647 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } | |
648 | #endif | |
3d2972fe | 649 | #endif |
b6240846 YS |
650 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 |
651 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
a4c955bc PK |
652 | #define CONFIG_SYS_FSL_SRDS_1 |
653 | #define CONFIG_SYS_FSL_SRDS_2 | |
b6240846 YS |
654 | #define CONFIG_SYS_FSL_SRDS_3 |
655 | #define CONFIG_SYS_FSL_SRDS_4 | |
656 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
657 | #define CONFIG_SYS_NUM_FMAN 2 | |
f1810d85 | 658 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ce746fe0 | 659 | #define CONFIG_SYS_PME_CLK 0 |
b6240846 | 660 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
362ee04b | 661 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
b6240846 | 662 | #define CONFIG_SYS_FMAN_V3 |
ce746fe0 PK |
663 | #define CONFIG_SYS_FM1_CLK 3 |
664 | #define CONFIG_SYS_FM2_CLK 3 | |
b6240846 YS |
665 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 |
666 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
667 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
668 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
669 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
670 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
08047937 | 671 | #define CONFIG_SYS_FSL_SRIO_LIODN |
b6240846 YS |
672 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE |
673 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
674 | #define CONFIG_SYS_FSL_ERRATUM_A004468 | |
675 | #define CONFIG_SYS_FSL_ERRATUM_A_004934 | |
676 | #define CONFIG_SYS_FSL_ERRATUM_A005871 | |
9c641a87 | 677 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
133fbfa9 | 678 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
b6808cd8 | 679 | #define CONFIG_SYS_FSL_ERRATUM_A007186 |
82125192 | 680 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
b6240846 | 681 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
b6808cd8 | 682 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
b6240846 YS |
683 | #define CONFIG_SYS_FSL_PCI_VER_3_X |
684 | ||
8fa0102b PA |
685 | #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) |
686 | #define CONFIG_E6500 | |
e1dbdd81 PA |
687 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
688 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
689 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
690 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ | |
e1dbdd81 | 691 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
a4c955bc PK |
692 | #define CONFIG_SYS_FSL_SRDS_1 |
693 | #define CONFIG_SYS_FSL_SRDS_2 | |
e1dbdd81 PA |
694 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
695 | #define CONFIG_SYS_NUM_FMAN 1 | |
f1810d85 | 696 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
ce746fe0 | 697 | #define CONFIG_SYS_FM1_CLK 0 |
e1dbdd81 | 698 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
362ee04b | 699 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 |
e1dbdd81 PA |
700 | #define CONFIG_SYS_FMAN_V3 |
701 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 | |
702 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
703 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
704 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
705 | #define CONFIG_SYS_FSL_ERRATUM_A_004934 | |
04feb57f | 706 | #define CONFIG_SYS_FSL_ERRATUM_A005871 |
133fbfa9 | 707 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
b6808cd8 | 708 | #define CONFIG_SYS_FSL_ERRATUM_A007186 |
82125192 | 709 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
11856919 | 710 | #define CONFIG_SYS_FSL_ERRATUM_A007075 |
7af9a074 SL |
711 | #define CONFIG_SYS_FSL_ERRATUM_A006475 |
712 | #define CONFIG_SYS_FSL_ERRATUM_A006384 | |
c3678b09 | 713 | #define CONFIG_SYS_FSL_ERRATUM_A007212 |
e1dbdd81 | 714 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
b6808cd8 | 715 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
e1dbdd81 | 716 | |
8fa0102b | 717 | #ifdef CONFIG_PPC_B4860 |
f6981439 | 718 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |
d2404141 | 719 | #define CONFIG_MAX_CPUS 4 |
6df82e3c | 720 | #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 |
d2404141 | 721 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
ce746fe0 | 722 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } |
d2404141 YS |
723 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 |
724 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
e394ceb1 | 725 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
f1810d85 | 726 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
d2404141 YS |
727 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
728 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
729 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
32f38ee3 | 730 | #define CONFIG_SYS_FSL_SRIO_LIODN |
8fa0102b PA |
731 | #else |
732 | #define CONFIG_MAX_CPUS 2 | |
6df82e3c | 733 | #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 |
8fa0102b PA |
734 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 |
735 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 | |
ce746fe0 | 736 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } |
8fa0102b PA |
737 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 |
738 | #define CONFIG_SYS_NUM_FM1_10GEC 0 | |
739 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
740 | #endif | |
d2404141 | 741 | |
2967af68 PJ |
742 | #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ |
743 | defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) | |
5f208d11 YS |
744 | #define CONFIG_E5500 |
745 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
746 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
f6981439 | 747 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 |
5f208d11 | 748 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ |
34e026f9 YS |
749 | #ifdef CONFIG_SYS_FSL_DDR4 |
750 | #define CONFIG_SYS_FSL_DDRC_GEN4 | |
751 | #endif | |
1d384eca | 752 | #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) |
5f208d11 | 753 | #define CONFIG_MAX_CPUS 4 |
1d384eca PK |
754 | #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) |
755 | #define CONFIG_MAX_CPUS 2 | |
756 | #endif | |
757 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
ce746fe0 PK |
758 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } |
759 | #define CONFIG_SYS_SDHC_CLOCK 0 | |
5f208d11 | 760 | #define CONFIG_SYS_FSL_NUM_LAWS 16 |
1d384eca PK |
761 | #define CONFIG_SYS_FSL_SRDS_1 |
762 | #define CONFIG_SYS_FSL_SEC_COMPAT 5 | |
5f208d11 YS |
763 | #define CONFIG_SYS_NUM_FMAN 1 |
764 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
765 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 766 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ce746fe0 PK |
767 | #define CONFIG_PME_PLAT_CLK_DIV 2 |
768 | #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV | |
1d384eca PK |
769 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 |
770 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
5f208d11 | 771 | #define CONFIG_SYS_FMAN_V3 |
ce746fe0 PK |
772 | #define CONFIG_FM_PLAT_CLK_DIV 1 |
773 | #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV | |
1d384eca | 774 | #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 |
b135991a | 775 | #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK |
e03c76c3 | 776 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
5f208d11 | 777 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" |
a4f7cba6 | 778 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE |
5f208d11 | 779 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
9c641a87 | 780 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
5f208d11 | 781 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
1336e2d3 HZ |
782 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
783 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE | |
2a44efeb ZQ |
784 | #define QE_MURAM_SIZE 0x6000UL |
785 | #define MAX_QE_RISC 1 | |
786 | #define QE_NUM_OF_SNUM 28 | |
5f208d11 | 787 | |
629d6b32 SL |
788 | #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) |
789 | #define CONFIG_E6500 | |
790 | #define CONFIG_SYS_PPC64 /* 64-bit core */ | |
791 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
792 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
793 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 | |
794 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
795 | #define CONFIG_SYS_FSL_QMAN_V3 | |
796 | #define CONFIG_MAX_CPUS 4 | |
797 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
798 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
799 | #define CONFIG_SYS_NUM_FMAN 1 | |
800 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } | |
801 | #define CONFIG_SYS_FSL_SRDS_1 | |
802 | #define CONFIG_SYS_FSL_PCI_VER_3_X | |
803 | #if defined(CONFIG_PPC_T2080) | |
804 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 | |
805 | #define CONFIG_SYS_NUM_FM1_10GEC 4 | |
806 | #define CONFIG_SYS_FSL_SRDS_2 | |
807 | #define CONFIG_SYS_FSL_SRIO_LIODN | |
808 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
809 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
810 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
811 | #elif defined(CONFIG_PPC_T2081) | |
812 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 | |
813 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
814 | #endif | |
2ffa96d8 | 815 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
629d6b32 SL |
816 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
817 | #define CONFIG_PME_PLAT_CLK_DIV 1 | |
818 | #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV | |
819 | #define CONFIG_SYS_FM1_CLK 0 | |
820 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 | |
821 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
822 | #define CONFIG_SYS_FMAN_V3 | |
823 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 | |
824 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
825 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
826 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE | |
827 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
c3678b09 | 828 | #define CONFIG_SYS_FSL_ERRATUM_A007212 |
629d6b32 SL |
829 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
830 | #define CONFIG_SYS_FSL_SFP_VER_3_0 | |
831 | #define CONFIG_SYS_FSL_ISBC_VER 2 | |
1336e2d3 | 832 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
c665c473 SL |
833 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
834 | #define CONFIG_SYS_FSL_ERRATUM_A006593 | |
b6808cd8 | 835 | #define CONFIG_SYS_FSL_ERRATUM_A007186 |
c665c473 | 836 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
1336e2d3 | 837 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
b6808cd8 | 838 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
1336e2d3 | 839 | |
629d6b32 | 840 | |
3b75e982 MH |
841 | #elif defined(CONFIG_PPC_C29X) |
842 | #define CONFIG_MAX_CPUS 1 | |
843 | #define CONFIG_FSL_SDHC_V2_3 | |
844 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
845 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 | |
846 | #define CONFIG_TSECV2_1 | |
847 | #define CONFIG_SYS_FSL_SEC_COMPAT 6 | |
848 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
849 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
34e026f9 | 850 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 |
3b75e982 MH |
851 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
852 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
954a1a47 | 853 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
3b75e982 | 854 | |
fa08d395 AG |
855 | #elif defined(CONFIG_QEMU_E500) |
856 | #define CONFIG_MAX_CPUS 1 | |
857 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 | |
858 | ||
243be8e2 KG |
859 | #else |
860 | #error Processor type not defined for this platform | |
861 | #endif | |
862 | ||
e46fedfe TT |
863 | #ifndef CONFIG_SYS_CCSRBAR_DEFAULT |
864 | #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." | |
865 | #endif | |
866 | ||
f6981439 YS |
867 | #ifdef CONFIG_E6500 |
868 | #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 | |
869 | #else | |
870 | #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 | |
871 | #endif | |
872 | ||
5614e71b YS |
873 | #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ |
874 | !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ | |
34e026f9 YS |
875 | !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ |
876 | !defined(CONFIG_SYS_FSL_DDRC_GEN4) | |
5614e71b YS |
877 | #define CONFIG_SYS_FSL_DDRC_GEN3 |
878 | #endif | |
879 | ||
243be8e2 | 880 | #endif /* _ASM_MPC85xx_CONFIG_H_ */ |