]>
Commit | Line | Data |
---|---|---|
243be8e2 | 1 | /* |
19a8dbdc | 2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. |
243be8e2 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
243be8e2 KG |
5 | */ |
6 | ||
7 | #ifndef _ASM_MPC85xx_CONFIG_H_ | |
8 | #define _ASM_MPC85xx_CONFIG_H_ | |
9 | ||
10 | /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ | |
11 | ||
2a5fcb83 YS |
12 | /* |
13 | * This macro should be removed when we no longer care about backwards | |
14 | * compatibility with older operating systems. | |
15 | */ | |
16 | #define CONFIG_PPC_SPINTABLE_COMPATIBLE | |
17 | ||
34e026f9 | 18 | #include <fsl_ddrc_version.h> |
57495e4e | 19 | |
1b4175d6 PK |
20 | /* IP endianness */ |
21 | #define CONFIG_SYS_FSL_IFC_BE | |
a2e225e6 | 22 | #define CONFIG_SYS_FSL_SFP_BE |
e04916a7 | 23 | #define CONFIG_SYS_FSL_SEC_MON_BE |
1b4175d6 | 24 | |
24ad75ae | 25 | #if defined(CONFIG_ARCH_MPC8536) |
9855b3be | 26 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 27 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 28 | |
7f825218 | 29 | #elif defined(CONFIG_ARCH_MPC8540) |
243be8e2 | 30 | |
3aff3082 | 31 | #elif defined(CONFIG_ARCH_MPC8541) |
243be8e2 | 32 | |
25cb74b3 | 33 | #elif defined(CONFIG_ARCH_MPC8544) |
954a1a47 | 34 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 35 | |
281ed4c7 | 36 | #elif defined(CONFIG_ARCH_MPC8548) |
5ace2992 | 37 | #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 |
2b3a1cdd | 38 | #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 |
aada81de | 39 | #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
7d67ed58 LG |
40 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
41 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
42 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
43 | #define CONFIG_SYS_FSL_RMU | |
44 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
954a1a47 | 45 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
46 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
47 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 | |
243be8e2 | 48 | |
3c3d8ab5 | 49 | #elif defined(CONFIG_ARCH_MPC8555) |
243be8e2 | 50 | |
99d0a312 | 51 | #elif defined(CONFIG_ARCH_MPC8560) |
243be8e2 | 52 | |
d07c3843 | 53 | #elif defined(CONFIG_ARCH_MPC8568) |
fdb4dad3 KG |
54 | #define QE_MURAM_SIZE 0x10000UL |
55 | #define MAX_QE_RISC 2 | |
56 | #define QE_NUM_OF_SNUM 28 | |
7d67ed58 LG |
57 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
58 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
59 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
60 | #define CONFIG_SYS_FSL_RMU | |
61 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
243be8e2 | 62 | |
23b36a7d | 63 | #elif defined(CONFIG_ARCH_MPC8569) |
fdb4dad3 KG |
64 | #define QE_MURAM_SIZE 0x20000UL |
65 | #define MAX_QE_RISC 4 | |
66 | #define QE_NUM_OF_SNUM 46 | |
7d67ed58 LG |
67 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
68 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
69 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
70 | #define CONFIG_SYS_FSL_RMU | |
71 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
9855b3be | 72 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 73 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 74 | |
c8f48474 | 75 | #elif defined(CONFIG_ARCH_MPC8572) |
eb0aff77 | 76 | #define CONFIG_SYS_FSL_ERRATUM_DDR_115 |
91671913 | 77 | #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 |
9855b3be | 78 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 79 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 80 | |
7d5f9f84 | 81 | #elif defined(CONFIG_ARCH_P1010) |
32c8cfb2 | 82 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 83 | #define CONFIG_TSECV2 |
1fbf3483 | 84 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
f1810d85 | 85 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
362ee04b | 86 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 |
8f29084a | 87 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
1b719e66 | 88 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 89 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 90 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
424bf942 | 91 | #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 |
bc6bbd6b | 92 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
954a1a47 | 93 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb | 94 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9855b3be | 95 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
11856919 | 96 | #define CONFIG_SYS_FSL_ERRATUM_A007075 |
15a6d496 | 97 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
9c641a87 | 98 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
0dc78ff8 | 99 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
9c3f77eb | 100 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 |
f28bea00 | 101 | #define CONFIG_ESDHC_HC_BLK_ADDR |
243be8e2 | 102 | |
093cffbe | 103 | /* P1011 is single core version of P1020 */ |
1cdd96f3 | 104 | #elif defined(CONFIG_ARCH_P1011) |
243be8e2 | 105 | #define CONFIG_TSECV2 |
b03a466d | 106 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
f1810d85 | 107 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
093cffbe | 108 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
9855b3be | 109 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 110 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
67a719da | 111 | |
484fff64 | 112 | #elif defined(CONFIG_ARCH_P1020) |
243be8e2 | 113 | #define CONFIG_TSECV2 |
b03a466d | 114 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
093cffbe | 115 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
9855b3be | 116 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 117 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
80ba6a6f | 118 | #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT |
f1810d85 | 119 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
80ba6a6f | 120 | #endif |
243be8e2 | 121 | |
a990799d | 122 | #elif defined(CONFIG_ARCH_P1021) |
243be8e2 | 123 | #define CONFIG_TSECV2 |
b03a466d | 124 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
093cffbe | 125 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
a52d2f81 HW |
126 | #define QE_MURAM_SIZE 0x6000UL |
127 | #define MAX_QE_RISC 1 | |
128 | #define QE_NUM_OF_SNUM 28 | |
9855b3be | 129 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 130 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1810d85 | 131 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
243be8e2 | 132 | |
feb9e25b | 133 | #elif defined(CONFIG_ARCH_P1022) |
243be8e2 | 134 | #define CONFIG_TSECV2 |
703f5681 | 135 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
2d7534a3 | 136 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
2d7534a3 | 137 | #define CONFIG_FSL_SATA_ERRATUM_A001 |
9855b3be | 138 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 139 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
0dc78ff8 | 140 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
243be8e2 | 141 | |
9bb1d6bc | 142 | #elif defined(CONFIG_ARCH_P1023) |
67a719da RZ |
143 | #define CONFIG_SYS_NUM_FMAN 1 |
144 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
145 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 146 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
67a719da RZ |
147 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 |
148 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 149 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 150 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
9855b3be | 151 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 152 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
153 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
154 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
67a719da | 155 | |
093cffbe | 156 | /* P1024 is lower end variant of P1020 */ |
52b6f13d | 157 | #elif defined(CONFIG_ARCH_P1024) |
093cffbe KG |
158 | #define CONFIG_TSECV2 |
159 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
f1810d85 | 160 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
093cffbe | 161 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
9855b3be | 162 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 163 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
093cffbe KG |
164 | |
165 | /* P1025 is lower end variant of P1021 */ | |
4167a67d | 166 | #elif defined(CONFIG_ARCH_P1025) |
1ff10a87 | 167 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
093cffbe KG |
168 | #define CONFIG_TSECV2 |
169 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
093cffbe | 170 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
a52d2f81 HW |
171 | #define QE_MURAM_SIZE 0x6000UL |
172 | #define MAX_QE_RISC 1 | |
173 | #define QE_NUM_OF_SNUM 28 | |
9855b3be | 174 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 175 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
093cffbe | 176 | |
4593637b | 177 | #elif defined(CONFIG_ARCH_P2020) |
7d67ed58 LG |
178 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
179 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
180 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
181 | #define CONFIG_SYS_FSL_RMU | |
182 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
9855b3be | 183 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 184 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
0dc78ff8 | 185 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
f1810d85 | 186 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
9855b3be | 187 | |
ce040c83 | 188 | #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ |
d1001e3f | 189 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 190 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
1f97987a | 191 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
1f97987a KG |
192 | #define CONFIG_SYS_NUM_FMAN 1 |
193 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
194 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
195 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 196 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
1f97987a KG |
197 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
198 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 | |
199 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
200 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
201 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 202 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
5e23ab0a | 203 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
99d7b0a4 | 204 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
43f082bb | 205 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
e22be77a | 206 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 207 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
208 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
209 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
210 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
211 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
212 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
213 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
214 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 215 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 216 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
9c3f77eb | 217 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 218 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 219 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 |
1f97987a | 220 | |
5e5fdd2d | 221 | #elif defined(CONFIG_ARCH_P3041) |
d1001e3f | 222 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 223 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
b5c8753f | 224 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
fbee0f7f KG |
225 | #define CONFIG_SYS_NUM_FMAN 1 |
226 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
227 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
228 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
34e026f9 | 229 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 |
c657d898 | 230 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 231 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 232 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
86221f09 RZ |
233 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
234 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 235 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
f1810d85 | 236 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
57125f22 | 237 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
99d7b0a4 | 238 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
43f082bb | 239 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
e22be77a | 240 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 241 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
242 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
243 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
244 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
245 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
246 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
247 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
248 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 249 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 250 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
d217a9ad | 251 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
9c3f77eb | 252 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 253 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 254 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 255 | |
e71372cb | 256 | #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ |
d1001e3f | 257 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 258 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
b5c8753f | 259 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
243be8e2 KG |
260 | #define CONFIG_SYS_NUM_FMAN 2 |
261 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
262 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 | |
263 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
264 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
265 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 266 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 267 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
c657d898 | 268 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 269 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
8f29084a | 270 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" |
243be8e2 KG |
271 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
272 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 | |
fa8d23c0 | 273 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
243be8e2 | 274 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
243be8e2 | 275 | #define CONFIG_SYS_P4080_ERRATUM_CPU22 |
5e23ab0a | 276 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
243be8e2 | 277 | #define CONFIG_SYS_P4080_ERRATUM_SERDES8 |
df8af0b4 | 278 | #define CONFIG_SYS_P4080_ERRATUM_SERDES9 |
d90fdba6 | 279 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
da30b9fd | 280 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 |
43f082bb | 281 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
4108508a | 282 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
283 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
284 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
285 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
286 | #define CONFIG_SYS_FSL_RMU | |
287 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
33eee330 SW |
288 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
289 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 | |
290 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 | |
d59c5570 | 291 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 292 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
d607b968 | 293 | #define CONFIG_SYS_FSL_ERRATUM_A004580 |
c0a4e6b8 | 294 | #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 |
d217a9ad | 295 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
9c3f77eb | 296 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
11856919 | 297 | #define CONFIG_SYS_FSL_ERRATUM_A007075 |
9c3f77eb | 298 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 299 | |
cefe11cd | 300 | #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ |
ffd06e02 | 301 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
d1001e3f | 302 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 303 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
b5c8753f | 304 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
fbee0f7f KG |
305 | #define CONFIG_SYS_NUM_FMAN 1 |
306 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
307 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
308 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 309 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 310 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
c657d898 | 311 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 312 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 313 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
86221f09 RZ |
314 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
315 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 316 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
99d7b0a4 | 317 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
e22be77a | 318 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 319 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
320 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
321 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
322 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
323 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
324 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
325 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 | |
d59c5570 | 326 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
9c3f77eb | 327 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 328 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 329 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 330 | |
95390360 | 331 | #elif defined(CONFIG_ARCH_P5040) |
1956e431 | 332 | #define CONFIG_SYS_PPC64 |
4905443f | 333 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 334 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
4905443f | 335 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 |
4905443f TT |
336 | #define CONFIG_SYS_NUM_FMAN 2 |
337 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
338 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
339 | #define CONFIG_SYS_NUM_FM2_DTSEC 5 | |
340 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
341 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 342 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 343 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
4905443f TT |
344 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
345 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
346 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
4905443f TT |
347 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
348 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
349 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
99d7b0a4 | 350 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
4905443f TT |
351 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
352 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 | |
353 | #define CONFIG_SYS_FSL_ERRATUM_A004699 | |
4905443f TT |
354 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
355 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
9c641a87 | 356 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
4905443f | 357 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 |
d217a9ad | 358 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
4905443f | 359 | |
115d60c0 | 360 | #elif defined(CONFIG_ARCH_BSC9131) |
19a8dbdc | 361 | #define CONFIG_FSL_SDHC_V2_3 |
19a8dbdc | 362 | #define CONFIG_TSECV2 |
19a8dbdc | 363 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
34e026f9 | 364 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 365 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
765b0bdb PJ |
366 | #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 |
367 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 | |
362ee04b | 368 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 |
19a8dbdc | 369 | #define CONFIG_NAND_FSL_IFC |
954a1a47 | 370 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
0dc78ff8 | 371 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
f28bea00 | 372 | #define CONFIG_ESDHC_HC_BLK_ADDR |
19a8dbdc | 373 | |
115d60c0 | 374 | #elif defined(CONFIG_ARCH_BSC9132) |
35fe948e | 375 | #define CONFIG_FSL_SDHC_V2_3 |
35fe948e | 376 | #define CONFIG_TSECV2 |
35fe948e | 377 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
34e026f9 | 378 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 |
f1810d85 | 379 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
64501c66 PJ |
380 | #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 |
381 | #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 | |
382 | #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 | |
383 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 | |
061ffeda | 384 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 |
35fe948e | 385 | #define CONFIG_NAND_FSL_IFC |
35fe948e PK |
386 | #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK |
387 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
954a1a47 | 388 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1a96ec1 | 389 | #define CONFIG_SYS_FSL_ERRATUM_A005434 |
0dc78ff8 | 390 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
9c3f77eb CL |
391 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
392 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
f28bea00 | 393 | #define CONFIG_ESDHC_HC_BLK_ADDR |
35fe948e | 394 | |
cdb72c52 | 395 | #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) |
3d2972fe | 396 | #define CONFIG_E6500 |
ffd06e02 | 397 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
9e758758 YS |
398 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
399 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
f6981439 | 400 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |
9e758758 | 401 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ |
26bc57da | 402 | #ifdef CONFIG_ARCH_T4240 |
ce746fe0 | 403 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } |
9e758758 YS |
404 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 |
405 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
406 | #define CONFIG_SYS_NUM_FM2_DTSEC 8 | |
407 | #define CONFIG_SYS_NUM_FM2_10GEC 2 | |
408 | #define CONFIG_NUM_DDR_CONTROLLERS 3 | |
f413d1ca | 409 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
3d2972fe | 410 | #else |
5122dfae | 411 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 |
3d2972fe | 412 | #define CONFIG_SYS_NUM_FM1_10GEC 1 |
5122dfae | 413 | #define CONFIG_SYS_NUM_FM2_DTSEC 8 |
3d2972fe YS |
414 | #define CONFIG_SYS_NUM_FM2_10GEC 1 |
415 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
652a7bbd | 416 | #if defined(CONFIG_ARCH_T4160) |
5122dfae | 417 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } |
5122dfae | 418 | #endif |
3d2972fe | 419 | #endif |
b6240846 | 420 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 |
a4c955bc PK |
421 | #define CONFIG_SYS_FSL_SRDS_1 |
422 | #define CONFIG_SYS_FSL_SRDS_2 | |
b6240846 YS |
423 | #define CONFIG_SYS_FSL_SRDS_3 |
424 | #define CONFIG_SYS_FSL_SRDS_4 | |
b6240846 | 425 | #define CONFIG_SYS_NUM_FMAN 2 |
f1810d85 | 426 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ce746fe0 | 427 | #define CONFIG_SYS_PME_CLK 0 |
b6240846 | 428 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
362ee04b | 429 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
b6240846 | 430 | #define CONFIG_SYS_FMAN_V3 |
ce746fe0 PK |
431 | #define CONFIG_SYS_FM1_CLK 3 |
432 | #define CONFIG_SYS_FM2_CLK 3 | |
b6240846 YS |
433 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 |
434 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
435 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
436 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
437 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
438 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
08047937 | 439 | #define CONFIG_SYS_FSL_SRIO_LIODN |
b6240846 YS |
440 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE |
441 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
442 | #define CONFIG_SYS_FSL_ERRATUM_A004468 | |
b6240846 | 443 | #define CONFIG_SYS_FSL_ERRATUM_A005871 |
133fbfa9 | 444 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
b6808cd8 | 445 | #define CONFIG_SYS_FSL_ERRATUM_A007186 |
82125192 | 446 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
f3dff695 | 447 | #define CONFIG_SYS_FSL_ERRATUM_A007798 |
473f1fc2 | 448 | #define CONFIG_SYS_FSL_ERRATUM_A009942 |
b6808cd8 | 449 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
b6240846 YS |
450 | #define CONFIG_SYS_FSL_PCI_VER_3_X |
451 | ||
b41f192b | 452 | #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) |
8fa0102b | 453 | #define CONFIG_E6500 |
e1dbdd81 PA |
454 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
455 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
456 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
457 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ | |
b8bf0adc SL |
458 | #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ |
459 | #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ | |
460 | #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ | |
a4c955bc PK |
461 | #define CONFIG_SYS_FSL_SRDS_1 |
462 | #define CONFIG_SYS_FSL_SRDS_2 | |
b8bf0adc SL |
463 | #define CONFIG_SYS_MAPLE |
464 | #define CONFIG_SYS_CPRI | |
465 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 | |
e1dbdd81 | 466 | #define CONFIG_SYS_NUM_FMAN 1 |
f1810d85 | 467 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
ce746fe0 | 468 | #define CONFIG_SYS_FM1_CLK 0 |
b8bf0adc SL |
469 | #define CONFIG_SYS_CPRI_CLK 3 |
470 | #define CONFIG_SYS_ULB_CLK 4 | |
471 | #define CONFIG_SYS_ETVPE_CLK 1 | |
e1dbdd81 | 472 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
362ee04b | 473 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 |
e1dbdd81 PA |
474 | #define CONFIG_SYS_FMAN_V3 |
475 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 | |
476 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
477 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
478 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
04feb57f | 479 | #define CONFIG_SYS_FSL_ERRATUM_A005871 |
133fbfa9 | 480 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
b6808cd8 | 481 | #define CONFIG_SYS_FSL_ERRATUM_A007186 |
82125192 | 482 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
11856919 | 483 | #define CONFIG_SYS_FSL_ERRATUM_A007075 |
7af9a074 SL |
484 | #define CONFIG_SYS_FSL_ERRATUM_A006475 |
485 | #define CONFIG_SYS_FSL_ERRATUM_A006384 | |
c3678b09 | 486 | #define CONFIG_SYS_FSL_ERRATUM_A007212 |
0dc78ff8 | 487 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
473f1fc2 | 488 | #define CONFIG_SYS_FSL_ERRATUM_A009942 |
b6808cd8 | 489 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
e1dbdd81 | 490 | |
3006ebc3 | 491 | #ifdef CONFIG_ARCH_B4860 |
f6981439 | 492 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |
b8bf0adc SL |
493 | #define CONFIG_MAX_DSP_CPUS 12 |
494 | #define CONFIG_NUM_DSP_CPUS 6 | |
6df82e3c | 495 | #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 |
ce746fe0 | 496 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } |
d2404141 YS |
497 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 |
498 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
e394ceb1 | 499 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
f1810d85 | 500 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
d2404141 YS |
501 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
502 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
503 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
32f38ee3 | 504 | #define CONFIG_SYS_FSL_SRIO_LIODN |
8fa0102b | 505 | #else |
b8bf0adc | 506 | #define CONFIG_MAX_DSP_CPUS 2 |
6df82e3c | 507 | #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 |
8fa0102b | 508 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 |
ce746fe0 | 509 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } |
8fa0102b PA |
510 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 |
511 | #define CONFIG_SYS_NUM_FM1_10GEC 0 | |
512 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
513 | #endif | |
d2404141 | 514 | |
08a37fd1 | 515 | #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) |
5f208d11 YS |
516 | #define CONFIG_E5500 |
517 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
518 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
f6981439 | 519 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 |
5f208d11 | 520 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ |
1d384eca | 521 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
ce746fe0 | 522 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } |
1d384eca | 523 | #define CONFIG_SYS_FSL_SRDS_1 |
5f208d11 YS |
524 | #define CONFIG_SYS_NUM_FMAN 1 |
525 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
526 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 527 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ce746fe0 PK |
528 | #define CONFIG_PME_PLAT_CLK_DIV 2 |
529 | #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV | |
1d384eca PK |
530 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 |
531 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
9f074e67 | 532 | #define CONFIG_SYS_FSL_ERRATUM_A008044 |
5f208d11 | 533 | #define CONFIG_SYS_FMAN_V3 |
ce746fe0 PK |
534 | #define CONFIG_FM_PLAT_CLK_DIV 1 |
535 | #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV | |
2d9ca2c7 YL |
536 | #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 |
537 | per rcw field value */ | |
538 | #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ | |
1d384eca | 539 | #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 |
b135991a | 540 | #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK |
e03c76c3 | 541 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
5f208d11 | 542 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" |
a4f7cba6 | 543 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE |
5f208d11 | 544 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
1336e2d3 | 545 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
2a44efeb ZQ |
546 | #define QE_MURAM_SIZE 0x6000UL |
547 | #define MAX_QE_RISC 1 | |
548 | #define QE_NUM_OF_SNUM 28 | |
e622d9ed | 549 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
a46b1852 | 550 | #define CONFIG_SYS_FSL_ERRATUM_A008378 |
a994b3de | 551 | #define CONFIG_SYS_FSL_ERRATUM_A009663 |
473f1fc2 | 552 | #define CONFIG_SYS_FSL_ERRATUM_A009942 |
5f208d11 | 553 | |
08a37fd1 | 554 | #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) |
f6050790 SL |
555 | #define CONFIG_E5500 |
556 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
557 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
558 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 | |
559 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ | |
560 | #define CONFIG_SYS_FMAN_V3 | |
f6050790 SL |
561 | #define CONFIG_SYS_FSL_NUM_CC_PLL 2 |
562 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } | |
f6050790 | 563 | #define CONFIG_SYS_FSL_SRDS_1 |
f6050790 SL |
564 | #define CONFIG_SYS_NUM_FMAN 1 |
565 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
566 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
cc19c25e | 567 | #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION |
f6050790 SL |
568 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
569 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
570 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 | |
571 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
572 | #define CONFIG_SYS_FM1_CLK 0 | |
2d9ca2c7 YL |
573 | #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 |
574 | per rcw field value */ | |
f6050790 SL |
575 | #define CONFIG_QBMAN_CLK_DIV 1 |
576 | #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 | |
577 | #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK | |
578 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
579 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
580 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE | |
581 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
f6050790 SL |
582 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
583 | #define QE_MURAM_SIZE 0x6000UL | |
584 | #define MAX_QE_RISC 1 | |
585 | #define QE_NUM_OF_SNUM 28 | |
586 | #define CONFIG_SYS_FSL_SFP_VER_3_0 | |
a46b1852 | 587 | #define CONFIG_SYS_FSL_ERRATUM_A008378 |
a994b3de | 588 | #define CONFIG_SYS_FSL_ERRATUM_A009663 |
473f1fc2 | 589 | #define CONFIG_SYS_FSL_ERRATUM_A009942 |
f6050790 | 590 | |
0f3d80e9 | 591 | #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) |
629d6b32 SL |
592 | #define CONFIG_E6500 |
593 | #define CONFIG_SYS_PPC64 /* 64-bit core */ | |
594 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
595 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
596 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 | |
597 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
598 | #define CONFIG_SYS_FSL_QMAN_V3 | |
629d6b32 SL |
599 | #define CONFIG_SYS_NUM_FMAN 1 |
600 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } | |
601 | #define CONFIG_SYS_FSL_SRDS_1 | |
602 | #define CONFIG_SYS_FSL_PCI_VER_3_X | |
0f3d80e9 | 603 | #if defined(CONFIG_ARCH_T2080) |
629d6b32 SL |
604 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 |
605 | #define CONFIG_SYS_NUM_FM1_10GEC 4 | |
606 | #define CONFIG_SYS_FSL_SRDS_2 | |
607 | #define CONFIG_SYS_FSL_SRIO_LIODN | |
608 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
609 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
610 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
0f3d80e9 | 611 | #elif defined(CONFIG_ARCH_T2081) |
629d6b32 SL |
612 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 |
613 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
614 | #endif | |
2ffa96d8 | 615 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
629d6b32 SL |
616 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
617 | #define CONFIG_PME_PLAT_CLK_DIV 1 | |
618 | #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV | |
619 | #define CONFIG_SYS_FM1_CLK 0 | |
2d9ca2c7 YL |
620 | #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 |
621 | per rcw field value */ | |
622 | #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ | |
629d6b32 SL |
623 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
624 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
625 | #define CONFIG_SYS_FMAN_V3 | |
626 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 | |
627 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
628 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
629 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE | |
630 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
c3678b09 | 631 | #define CONFIG_SYS_FSL_ERRATUM_A007212 |
629d6b32 SL |
632 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
633 | #define CONFIG_SYS_FSL_ISBC_VER 2 | |
c665c473 | 634 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
b6808cd8 | 635 | #define CONFIG_SYS_FSL_ERRATUM_A007186 |
c665c473 | 636 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
473f1fc2 | 637 | #define CONFIG_SYS_FSL_ERRATUM_A009942 |
1336e2d3 | 638 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
b6808cd8 | 639 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
1336e2d3 | 640 | |
629d6b32 | 641 | |
4fd64746 | 642 | #elif defined(CONFIG_ARCH_C29X) |
3b75e982 | 643 | #define CONFIG_FSL_SDHC_V2_3 |
3b75e982 | 644 | #define CONFIG_TSECV2_1 |
3b75e982 | 645 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
34e026f9 | 646 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 |
3b75e982 | 647 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
954a1a47 | 648 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
404bf454 AP |
649 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 |
650 | #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 | |
3b75e982 | 651 | |
10343403 | 652 | #elif defined(CONFIG_ARCH_QEMU_E500) |
fa08d395 | 653 | |
243be8e2 KG |
654 | #else |
655 | #error Processor type not defined for this platform | |
656 | #endif | |
657 | ||
f6981439 YS |
658 | #ifdef CONFIG_E6500 |
659 | #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 | |
660 | #else | |
661 | #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 | |
662 | #endif | |
663 | ||
4fd64746 | 664 | #if !defined(CONFIG_ARCH_C29X) |
404bf454 AP |
665 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 |
666 | #endif | |
667 | ||
243be8e2 | 668 | #endif /* _ASM_MPC85xx_CONFIG_H_ */ |