[people/ms/u-boot.git] / arch / powerpc / include / asm / fsl_dma.h

/*
 * Freescale DMA Controller
 *
 * Copyright 2006 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#ifndef _ASM_FSL_DMA_H_
#define _ASM_FSL_DMA_H_

#include <asm/types.h>

#ifdef CONFIG_MPC83xx
typedef struct fsl_dma {
	uint	mr;		/* DMA mode register */
#define FSL_DMA_MR_CS		0x00000001	/* Channel start */
#define FSL_DMA_MR_CC		0x00000002	/* Channel continue */
#define FSL_DMA_MR_CTM		0x00000004	/* Channel xfer mode */
#define FSL_DMA_MR_CTM_DIRECT	0x00000004	/* Direct channel xfer mode */
#define FSL_DMA_MR_EOTIE	0x00000080	/* End-of-transfer interrupt en */
#define FSL_DMA_MR_PRC_MASK	0x00000c00	/* PCI read command */
#define FSL_DMA_MR_SAHE		0x00001000	/* Source addr hold enable */
#define FSL_DMA_MR_DAHE		0x00002000	/* Dest addr hold enable */
#define FSL_DMA_MR_SAHTS_MASK	0x0000c000	/* Source addr hold xfer size */
#define FSL_DMA_MR_DAHTS_MASK	0x00030000	/* Dest addr hold xfer size */
#define FSL_DMA_MR_EMS_EN	0x00040000	/* Ext master start en */
#define FSL_DMA_MR_IRQS		0x00080000	/* Interrupt steer */
#define FSL_DMA_MR_DMSEN	0x00100000	/* Direct mode snooping en */
#define FSL_DMA_MR_BWC_MASK	0x00e00000	/* Bandwidth/pause ctl */
#define FSL_DMA_MR_DRCNT	0x0f000000	/* DMA request count */
	uint	sr;		/* DMA status register */
#define FSL_DMA_SR_EOCDI	0x00000001	/* End-of-chain/direct interrupt */
#define FSL_DMA_SR_EOSI		0x00000002	/* End-of-segment interrupt */
#define FSL_DMA_SR_CB		0x00000004	/* Channel busy */
#define FSL_DMA_SR_TE		0x00000080	/* Transfer error */
	uint	cdar;		/* DMA current descriptor address register */
	char	res0[4];
	uint	sar;		/* DMA source address register */
	char	res1[4];
	uint	dar;		/* DMA destination address register */
	char	res2[4];
	uint	bcr;		/* DMA byte count register */
	uint	ndar;		/* DMA next descriptor address register */
	uint	gsr;		/* DMA general status register (DMA3 ONLY!) */
	char	res3[84];
} fsl_dma_t;
#else
typedef struct fsl_dma {
	uint	mr;		/* DMA mode register */
#define FSL_DMA_MR_CS		0x00000001	/* Channel start */
#define FSL_DMA_MR_CC		0x00000002	/* Channel continue */
#define FSL_DMA_MR_CTM		0x00000004	/* Channel xfer mode */
#define FSL_DMA_MR_CTM_DIRECT	0x00000004	/* Direct channel xfer mode */
#define FSL_DMA_MR_CA		0x00000008	/* Channel abort */
#define FSL_DMA_MR_CDSM		0x00000010
#define FSL_DMA_MR_XFE		0x00000020	/* Extended features en */
#define FSL_DMA_MR_EIE		0x00000040	/* Error interrupt en */
#define FSL_DMA_MR_EOLSIE	0x00000080	/* End-of-lists interrupt en */
#define FSL_DMA_MR_EOLNIE	0x00000100	/* End-of-links interrupt en */
#define FSL_DMA_MR_EOSIE	0x00000200	/* End-of-seg interrupt en */
#define FSL_DMA_MR_SRW		0x00000400	/* Single register write */
#define FSL_DMA_MR_SAHE		0x00001000	/* Source addr hold enable */
#define FSL_DMA_MR_DAHE		0x00002000	/* Dest addr hold enable */
#define FSL_DMA_MR_SAHTS_MASK	0x0000c000	/* Source addr hold xfer size */
#define FSL_DMA_MR_DAHTS_MASK	0x00030000	/* Dest addr hold xfer size */
#define FSL_DMA_MR_EMS_EN	0x00040000	/* Ext master start en */
#define FSL_DMA_MR_EMP_EN	0x00200000	/* Ext master pause en */
#define FSL_DMA_MR_BWC_MASK	0x0f000000	/* Bandwidth/pause ctl */
#define FSL_DMA_MR_BWC_DIS	0x0f000000	/* Bandwidth/pause ctl disable */
	uint	sr;		/* DMA status register */
#define FSL_DMA_SR_EOLSI	0x00000001	/* End-of-list interrupt */
#define FSL_DMA_SR_EOSI		0x00000002	/* End-of-segment interrupt */
#define FSL_DMA_SR_CB		0x00000004	/* Channel busy */
#define FSL_DMA_SR_EOLNI	0x00000008	/* End-of-links interrupt */
#define FSL_DMA_SR_PE		0x00000010	/* Programming error */
#define FSL_DMA_SR_CH		0x00000020	/* Channel halted */
#define FSL_DMA_SR_TE		0x00000080	/* Transfer error */
	char	res0[4];
	uint	clndar;		/* DMA current link descriptor address register */
	uint	satr;		/* DMA source attributes register */
#define FSL_DMA_SATR_ESAD_MASK		0x000001ff	/* Extended source addr */
#define FSL_DMA_SATR_SREAD_NO_SNOOP	0x00040000	/* Read, don't snoop */
#define FSL_DMA_SATR_SREAD_SNOOP	0x00050000	/* Read, snoop */
#define FSL_DMA_SATR_SREAD_UNLOCK	0x00070000	/* Read, unlock l2 */
#define FSL_DMA_SATR_STRAN_MASK		0x00f00000	/* Source interface  */
#define FSL_DMA_SATR_SSME		0x01000000	/* Source stride en */
#define FSL_DMA_SATR_SPCIORDER		0x02000000	/* PCI transaction order */
#define FSL_DMA_SATR_STFLOWLVL_MASK	0x0c000000	/* RIO flow level */
#define FSL_DMA_SATR_SBPATRMU		0x20000000	/* Bypass ATMU */
	uint	sar;		/* DMA source address register */
	uint	datr;		/* DMA destination attributes register */
#define FSL_DMA_DATR_EDAD_MASK		0x000001ff	/* Extended dest addr */
#define FSL_DMA_DATR_DWRITE_NO_SNOOP	0x00040000	/* Write, don't snoop */
#define FSL_DMA_DATR_DWRITE_SNOOP	0x00050000	/* Write, snoop */
#define FSL_DMA_DATR_DWRITE_ALLOC	0x00060000	/* Write, alloc l2 */
#define FSL_DMA_DATR_DWRITE_LOCK	0x00070000	/* Write, lock l2 */
#define FSL_DMA_DATR_DTRAN_MASK		0x00f00000	/* Dest interface  */
#define FSL_DMA_DATR_DSME		0x01000000	/* Dest stride en */
#define FSL_DMA_DATR_DPCIORDER		0x02000000	/* PCI transaction order */
#define FSL_DMA_DATR_DTFLOWLVL_MASK	0x0c000000	/* RIO flow level */
#define FSL_DMA_DATR_DBPATRMU		0x20000000	/* Bypass ATMU */
	uint	dar;		/* DMA destination address register */
	uint	bcr;		/* DMA byte count register */
	char	res1[4];
	uint	nlndar;		/* DMA next link descriptor address register */
	char	res2[8];
	uint	clabdar;	/* DMA current List - alternate base descriptor address Register */
	char	res3[4];
	uint	nlsdar;		/* DMA next list descriptor address register */
	uint	ssr;		/* DMA source stride register */
	uint	dsr;		/* DMA destination stride register */
	char	res4[56];
} fsl_dma_t;
#endif /* !CONFIG_MPC83xx */

#ifdef CONFIG_FSL_DMA
void dma_init(void);
int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
void dma_meminit(uint val, uint size);
#endif
#endif

#endif	/* _ASM_DMA_H_ */
Commit	Line	Data
b1f12650 PT	1	/*
	2	* Freescale DMA Controller
	3	*
	4	* Copyright 2006 Freescale Semiconductor, Inc.
	5	*
5b8031cc	6	* SPDX-License-Identifier: GPL-2.0
b1f12650 PT	7	*/
	8
	9	#ifndef _ASM_FSL_DMA_H_
	10	#define _ASM_FSL_DMA_H_
	11
	12	#include <asm/types.h>
	13
e94e460c PT	14	#ifdef CONFIG_MPC83xx
	15	typedef struct fsl_dma {
	16	uint mr; /* DMA mode register */
	17	#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
	18	#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
	19	#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
	20	#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
	21	#define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
	22	#define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
	23	#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
	24	#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
	25	#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
	26	#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
	27	#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
	28	#define FSL_DMA_MR_IRQS 0x00080000 /* Interrupt steer */
	29	#define FSL_DMA_MR_DMSEN 0x00100000 /* Direct mode snooping en */
	30	#define FSL_DMA_MR_BWC_MASK 0x00e00000 /* Bandwidth/pause ctl */
	31	#define FSL_DMA_MR_DRCNT 0x0f000000 /* DMA request count */
	32	uint sr; /* DMA status register */
	33	#define FSL_DMA_SR_EOCDI 0x00000001 /* End-of-chain/direct interrupt */
	34	#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
	35	#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
	36	#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
	37	uint cdar; /* DMA current descriptor address register */
	38	char res0[4];
	39	uint sar; /* DMA source address register */
	40	char res1[4];
	41	uint dar; /* DMA destination address register */
	42	char res2[4];
	43	uint bcr; /* DMA byte count register */
	44	uint ndar; /* DMA next descriptor address register */
	45	uint gsr; /* DMA general status register (DMA3 ONLY!) */
	46	char res3[84];
	47	} fsl_dma_t;
	48	#else
b1f12650 PT	49	typedef struct fsl_dma {
b1f12650 PT	50	uint mr; /* DMA mode register */
9c06071a PT	51	#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
	52	#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
	53	#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
	54	#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
	55	#define FSL_DMA_MR_CA 0x00000008 /* Channel abort */
	56	#define FSL_DMA_MR_CDSM 0x00000010
	57	#define FSL_DMA_MR_XFE 0x00000020 /* Extended features en */
	58	#define FSL_DMA_MR_EIE 0x00000040 /* Error interrupt en */
	59	#define FSL_DMA_MR_EOLSIE 0x00000080 /* End-of-lists interrupt en */
	60	#define FSL_DMA_MR_EOLNIE 0x00000100 /* End-of-links interrupt en */
	61	#define FSL_DMA_MR_EOSIE 0x00000200 /* End-of-seg interrupt en */
	62	#define FSL_DMA_MR_SRW 0x00000400 /* Single register write */
	63	#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
	64	#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
	65	#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
	66	#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
	67	#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
	68	#define FSL_DMA_MR_EMP_EN 0x00200000 /* Ext master pause en */
	69	#define FSL_DMA_MR_BWC_MASK 0x0f000000 /* Bandwidth/pause ctl */
	70	#define FSL_DMA_MR_BWC_DIS 0x0f000000 /* Bandwidth/pause ctl disable */
b1f12650	71	uint sr; /* DMA status register */
9c06071a PT	72	#define FSL_DMA_SR_EOLSI 0x00000001 /* End-of-list interrupt */
	73	#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
	74	#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
	75	#define FSL_DMA_SR_EOLNI 0x00000008 /* End-of-links interrupt */
	76	#define FSL_DMA_SR_PE 0x00000010 /* Programming error */
	77	#define FSL_DMA_SR_CH 0x00000020 /* Channel halted */
	78	#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
b1f12650 PT	79	char res0[4];
	80	uint clndar; /* DMA current link descriptor address register */
	81	uint satr; /* DMA source attributes register */
9c06071a PT	82	#define FSL_DMA_SATR_ESAD_MASK 0x000001ff /* Extended source addr */
	83	#define FSL_DMA_SATR_SREAD_NO_SNOOP 0x00040000 /* Read, don't snoop */
	84	#define FSL_DMA_SATR_SREAD_SNOOP 0x00050000 /* Read, snoop */
	85	#define FSL_DMA_SATR_SREAD_UNLOCK 0x00070000 /* Read, unlock l2 */
	86	#define FSL_DMA_SATR_STRAN_MASK 0x00f00000 /* Source interface */
	87	#define FSL_DMA_SATR_SSME 0x01000000 /* Source stride en */
	88	#define FSL_DMA_SATR_SPCIORDER 0x02000000 /* PCI transaction order */
	89	#define FSL_DMA_SATR_STFLOWLVL_MASK 0x0c000000 /* RIO flow level */
	90	#define FSL_DMA_SATR_SBPATRMU 0x20000000 /* Bypass ATMU */
b1f12650 PT	91	uint sar; /* DMA source address register */
b1f12650 PT	92	uint datr; /* DMA destination attributes register */
9c06071a PT	93	#define FSL_DMA_DATR_EDAD_MASK 0x000001ff /* Extended dest addr */
	94	#define FSL_DMA_DATR_DWRITE_NO_SNOOP 0x00040000 /* Write, don't snoop */
	95	#define FSL_DMA_DATR_DWRITE_SNOOP 0x00050000 /* Write, snoop */
	96	#define FSL_DMA_DATR_DWRITE_ALLOC 0x00060000 /* Write, alloc l2 */
	97	#define FSL_DMA_DATR_DWRITE_LOCK 0x00070000 /* Write, lock l2 */
	98	#define FSL_DMA_DATR_DTRAN_MASK 0x00f00000 /* Dest interface */
	99	#define FSL_DMA_DATR_DSME 0x01000000 /* Dest stride en */
	100	#define FSL_DMA_DATR_DPCIORDER 0x02000000 /* PCI transaction order */
	101	#define FSL_DMA_DATR_DTFLOWLVL_MASK 0x0c000000 /* RIO flow level */
	102	#define FSL_DMA_DATR_DBPATRMU 0x20000000 /* Bypass ATMU */
b1f12650 PT	103	uint dar; /* DMA destination address register */
	104	uint bcr; /* DMA byte count register */
	105	char res1[4];
	106	uint nlndar; /* DMA next link descriptor address register */
	107	char res2[8];
	108	uint clabdar; /* DMA current List - alternate base descriptor address Register */
	109	char res3[4];
	110	uint nlsdar; /* DMA next list descriptor address register */
	111	uint ssr; /* DMA source stride register */
	112	uint dsr; /* DMA destination stride register */
	113	char res4[56];
	114	} fsl_dma_t;
e94e460c	115	#endif /* !CONFIG_MPC83xx */
b1f12650	116
191c7118 PT	117	#ifdef CONFIG_FSL_DMA
	118	void dma_init(void);
	119	int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
0d595f76 PT	120	#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
	121	void dma_meminit(uint val, uint size);
	122	#endif
191c7118 PT	123	#endif
191c7118 PT	124
b1f12650	125	#endif /* _ASM_DMA_H_ */