[people/ms/u-boot.git] / arch / powerpc / include / asm / fsl_pci.h

/*
 * Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __FSL_PCI_H_
#define __FSL_PCI_H_

#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <pci.h>

#define PEX_IP_BLK_REV_2_2	0x02080202
#define PEX_IP_BLK_REV_2_3	0x02080203
#define PEX_IP_BLK_REV_3_0	0x02080300

/* Freescale-specific PCI config registers */
#define FSL_PCI_PBFR		0x44

#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
/* Currently only the PCIe capability is used, so hardcode the offset.
 * if more capabilities need to be justified, the capability link method
 * should be applied here
 */
#define FSL_PCIE_CAP_ID		0x70
#define PCI_DCR		0x78    /* PCIe Device Control Register */
#define PCI_DSR		0x7a    /* PCIe Device Status Register */
#define PCI_LSR		0x82    /* PCIe Link Status Register */
#define PCI_LCR		0x80    /* PCIe Link Control Register */
#else
#define FSL_PCIE_CAP_ID		0x4c
#define PCI_DCR		0x54    /* PCIe Device Control Register */
#define PCI_DSR		0x56    /* PCIe Device Status Register */
#define PCI_LSR		0x5e    /* PCIe Link Status Register */
#define PCI_LCR		0x5c    /* PCIe Link Control Register */
#endif

#define FSL_PCIE_CFG_RDY	0x4b0
#define FSL_PROG_IF_AGENT	0x1

#define PCI_LTSSM	0x404   /* PCIe Link Training, Status State Machine */
#define  PCI_LTSSM_L0	0x16    /* L0 state */

int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
void fsl_pci_config_unlock(struct pci_controller *hose);
void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);

/*
 * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
 */

/*
 * PCI Translation Registers
 */
typedef struct pci_outbound_window {
	u32	potar;		/* 0x00 - Address */
	u32	potear;		/* 0x04 - Address Extended */
	u32	powbar;		/* 0x08 - Window Base Address */
	u32	res1;
	u32	powar;		/* 0x10 - Window Attributes */
#define POWAR_EN	0x80000000
#define POWAR_IO_READ	0x00080000
#define POWAR_MEM_READ	0x00040000
#define POWAR_IO_WRITE	0x00008000
#define POWAR_MEM_WRITE	0x00004000
	u32	res2[3];
} pot_t;

typedef struct pci_inbound_window {
	u32	pitar;		/* 0x00 - Address */
	u32	res1;
	u32	piwbar;		/* 0x08 - Window Base Address */
	u32	piwbear;	/* 0x0c - Window Base Address Extended */
	u32	piwar;		/* 0x10 - Window Attributes */
#define PIWAR_EN		0x80000000
#define PIWAR_PF		0x20000000
#define PIWAR_LOCAL		0x00f00000
#define PIWAR_READ_SNOOP	0x00050000
#define PIWAR_WRITE_SNOOP	0x00005000
	u32	res2[3];
} pit_t;

/* PCI/PCI Express Registers */
typedef struct ccsr_pci {
	u32	cfg_addr;	/* 0x000 - PCI Configuration Address Register */
	u32	cfg_data;	/* 0x004 - PCI Configuration Data Register */
	u32	int_ack;	/* 0x008 - PCI Interrupt Acknowledge Register */
	u32	out_comp_to;	/* 0x00C - PCI Outbound Completion Timeout Register */
	u32	out_conf_to;	/* 0x010 - PCI Configuration Timeout Register */
	u32	config;		/* 0x014 - PCIE CONFIG Register */
	u32	int_status;	/* 0x018 - PCIE interrupt status register */
	char	res2[4];
	u32	pme_msg_det;	/* 0x020 - PCIE PME & message detect register */
	u32	pme_msg_dis;	/* 0x024 - PCIE PME & message disable register */
	u32	pme_msg_int_en;	/* 0x028 - PCIE PME & message interrupt enable register */
	u32	pm_command;	/* 0x02c - PCIE PM Command register */
	char	res4[3016];	/*     (- #xbf8	 #x30)3016 */
	u32	block_rev1;	/* 0xbf8 - PCIE Block Revision register 1 */
	u32	block_rev2;	/* 0xbfc - PCIE Block Revision register 2 */

	pot_t	pot[5];		/* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
	u32	res5[24];
	pit_t	pmit;		/* 0xd00 - 0xd9c Inbound ATMU's MSI */
	u32	res6[24];
	pit_t	pit[4];		/* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */

#define PIT3 0
#define PIT2 1
#define PIT1 2

#if 0
	u32	potar0;		/* 0xc00 - PCI Outbound Transaction Address Register 0 */
	u32	potear0;	/* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
	char	res5[8];
	u32	powar0;		/* 0xc10 - PCI Outbound Window Attributes Register 0 */
	char	res6[12];
	u32	potar1;		/* 0xc20 - PCI Outbound Transaction Address Register 1 */
	u32	potear1;	/* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
	u32	powbar1;	/* 0xc28 - PCI Outbound Window Base Address Register 1 */
	char	res7[4];
	u32	powar1;		/* 0xc30 - PCI Outbound Window Attributes Register 1 */
	char	res8[12];
	u32	potar2;		/* 0xc40 - PCI Outbound Transaction Address Register 2 */
	u32	potear2;	/* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
	u32	powbar2;	/* 0xc48 - PCI Outbound Window Base Address Register 2 */
	char	res9[4];
	u32	powar2;		/* 0xc50 - PCI Outbound Window Attributes Register 2 */
	char	res10[12];
	u32	potar3;		/* 0xc60 - PCI Outbound Transaction Address Register 3 */
	u32	potear3;	/* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
	u32	powbar3;	/* 0xc68 - PCI Outbound Window Base Address Register 3 */
	char	res11[4];
	u32	powar3;		/* 0xc70 - PCI Outbound Window Attributes Register 3 */
	char	res12[12];
	u32	potar4;		/* 0xc80 - PCI Outbound Transaction Address Register 4 */
	u32	potear4;	/* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
	u32	powbar4;	/* 0xc88 - PCI Outbound Window Base Address Register 4 */
	char	res13[4];
	u32	powar4;		/* 0xc90 - PCI Outbound Window Attributes Register 4 */
	char	res14[268];
	u32	pitar3;		/* 0xda0 - PCI Inbound Translation Address Register 3 */
	char	res15[4];
	u32	piwbar3;	/* 0xda8 - PCI Inbound Window Base Address Register 3 */
	u32	piwbear3;	/* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
	u32	piwar3;		/* 0xdb0 - PCI Inbound Window Attributes Register 3 */
	char	res16[12];
	u32	pitar2;		/* 0xdc0 - PCI Inbound Translation Address Register 2 */
	char	res17[4];
	u32	piwbar2;	/* 0xdc8 - PCI Inbound Window Base Address Register 2 */
	u32	piwbear2;	/* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
	u32	piwar2;		/* 0xdd0 - PCI Inbound Window Attributes Register 2 */
	char	res18[12];
	u32	pitar1;		/* 0xde0 - PCI Inbound Translation Address Register 1 */
	char	res19[4];
	u32	piwbar1;	/* 0xde8 - PCI Inbound Window Base Address Register 1 */
	char	res20[4];
	u32	piwar1;		/* 0xdf0 - PCI Inbound Window Attributes Register 1 */
	char	res21[12];
#endif
	u32	pedr;		/* 0xe00 - PCI Error Detect Register */
	u32	pecdr;		/* 0xe04 - PCI Error Capture Disable Register */
	u32	peer;		/* 0xe08 - PCI Error Interrupt Enable Register */
	u32	peattrcr;	/* 0xe0c - PCI Error Attributes Capture Register */
	u32	peaddrcr;	/* 0xe10 - PCI Error Address Capture Register */
/*	u32	perr_disr	 * 0xe10 - PCIE Erorr Disable Register */
	u32	peextaddrcr;	/* 0xe14 - PCI	Error Extended Address Capture Register */
	u32	pedlcr;		/* 0xe18 - PCI Error Data Low Capture Register */
	u32	pedhcr;		/* 0xe1c - PCI Error Error Data High Capture Register */
	u32	gas_timr;	/* 0xe20 - PCI Gasket Timer Register */
/*	u32	perr_cap_stat;	 * 0xe20 - PCIE Error Capture Status Register */
	char	res22[4];
	u32	perr_cap0;	/* 0xe28 - PCIE Error Capture Register 0 */
	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
	char	res23[200];
	u32	pdb_stat;	/* 0xf00 - PCIE Debug Status */
	char	res24[16];
	u32	pex_csr0;	/* 0xf14 - PEX Control/Status register 0*/
	u32	pex_csr1;	/* 0xf18 - PEX Control/Status register 1*/
	char	res25[228];
} ccsr_fsl_pci_t;
#define PCIE_CONFIG_PC	0x00020000
#define PCIE_CONFIG_OB_CK	0x00002000
#define PCIE_CONFIG_SAC	0x00000010
#define PCIE_CONFIG_SP	0x80000002
#define PCIE_CONFIG_SCC	0x80000001

struct fsl_pci_info {
	unsigned long regs;
	pci_addr_t mem_bus;
	phys_size_t mem_phys;
	pci_size_t mem_size;
	pci_addr_t io_bus;
	phys_size_t io_phys;
	pci_size_t io_size;
	enum law_trgt_if law;
	int pci_num;
};

void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info);
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
				struct pci_controller *hose, int busno);
int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
			struct fsl_pci_info *pci_info);
int fsl_pcie_init_board(int busno);

#define SET_STD_PCI_INFO(x, num) \
{			\
	x.regs = CONFIG_SYS_PCI##num##_ADDR;	\
	x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
	x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
	x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
	x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
	x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
	x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
	x.law = LAW_TRGT_IF_PCI_##num; \
	x.pci_num = num; \
}

#define SET_STD_PCIE_INFO(x, num) \
{			\
	x.regs = CONFIG_SYS_PCIE##num##_ADDR;	\
	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
	x.law = LAW_TRGT_IF_PCIE_##num; \
	x.pci_num = num; \
}

#define __FT_FSL_PCI_SETUP(blob, compat, num) \
	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)

#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)

#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)

#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)

#if !defined(CONFIG_PCI)
#define FT_FSL_PCI_SETUP
#elif defined(CONFIG_FSL_CORENET)
#define FSL_PCIE_COMPAT	CONFIG_SYS_FSL_PCIE_COMPAT
#define FT_FSL_PCI_SETUP \
	FT_FSL_PCIE1_SETUP; \
	FT_FSL_PCIE2_SETUP; \
	FT_FSL_PCIE3_SETUP; \
	FT_FSL_PCIE4_SETUP;
#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
#elif defined(CONFIG_MPC85xx)
#define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
#define FSL_PCIE_COMPAT	CONFIG_SYS_FSL_PCIE_COMPAT
#else
#define FSL_PCIE_COMPAT	"fsl,mpc8548-pcie"
#endif
#define FT_FSL_PCI_SETUP \
	FT_FSL_PCI1_SETUP; \
	FT_FSL_PCI2_SETUP; \
	FT_FSL_PCIE1_SETUP; \
	FT_FSL_PCIE2_SETUP; \
	FT_FSL_PCIE3_SETUP;
#define FT_FSL_PCIE_SETUP \
	FT_FSL_PCIE1_SETUP; \
	FT_FSL_PCIE2_SETUP; \
	FT_FSL_PCIE3_SETUP;
#elif defined(CONFIG_MPC86xx)
#define FSL_PCI_COMPAT	"fsl,mpc8610-pci"
#define FSL_PCIE_COMPAT	"fsl,mpc8641-pcie"
#define FT_FSL_PCI_SETUP \
	FT_FSL_PCI1_SETUP; \
	FT_FSL_PCIE1_SETUP; \
	FT_FSL_PCIE2_SETUP;
#else
#error FT_FSL_PCI_SETUP not defined
#endif


#endif
Commit	Line	Data
ee53650d	1	/*
7b4e5844	2	* Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
63cec581	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
63cec581 ES	5	*/
63cec581 ES	6
32049b40 KG	7	#ifndef __FSL_PCI_H_
	8	#define __FSL_PCI_H_
	9
3e7b6c1f	10	#include <asm/fsl_law.h>
a4aafcc9 KG	11	#include <asm/fsl_serdes.h>
a4aafcc9 KG	12	#include <pci.h>
3e7b6c1f	13
b6ccd2c9 PK	14	#define PEX_IP_BLK_REV_2_2 0x02080202
b6ccd2c9 PK	15	#define PEX_IP_BLK_REV_2_3 0x02080203
7b4e5844 ZRR	16	#define PEX_IP_BLK_REV_3_0 0x02080300
	17
	18	/* Freescale-specific PCI config registers */
	19	#define FSL_PCI_PBFR 0x44
	20
	21	#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
	22	/* Currently only the PCIe capability is used, so hardcode the offset.
	23	* if more capabilities need to be justified, the capability link method
	24	* should be applied here
	25	*/
	26	#define FSL_PCIE_CAP_ID 0x70
	27	#define PCI_DCR 0x78 /* PCIe Device Control Register */
	28	#define PCI_DSR 0x7a /* PCIe Device Status Register */
	29	#define PCI_LSR 0x82 /* PCIe Link Status Register */
	30	#define PCI_LCR 0x80 /* PCIe Link Control Register */
	31	#else
	32	#define FSL_PCIE_CAP_ID 0x4c
	33	#define PCI_DCR 0x54 /* PCIe Device Control Register */
	34	#define PCI_DSR 0x56 /* PCIe Device Status Register */
	35	#define PCI_LSR 0x5e /* PCIe Link Status Register */
	36	#define PCI_LCR 0x5c /* PCIe Link Control Register */
	37	#endif
	38
	39	#define FSL_PCIE_CFG_RDY 0x4b0
	40	#define FSL_PROG_IF_AGENT 0x1
	41
	42	#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
	43	#define PCI_LTSSM_L0 0x16 /* L0 state */
b6ccd2c9	44
ee53650d	45	int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
715d8f76	46	int fsl_is_pci_agent(struct pci_controller *hose);
32049b40	47	void fsl_pci_config_unlock(struct pci_controller *hose);
3a0e3c27	48	void ft_fsl_pci_setup(void blob, const char compat, unsigned long ctrl_addr);
63cec581 ES	49
	50	/*
	51	* Common PCI/PCIE Register structure for mpc85xx and mpc86xx
	52	*/
	53
	54	/*
	55	* PCI Translation Registers
	56	*/
	57	typedef struct pci_outbound_window {
	58	u32 potar; /* 0x00 - Address */
	59	u32 potear; /* 0x04 - Address Extended */
	60	u32 powbar; /* 0x08 - Window Base Address */
	61	u32 res1;
	62	u32 powar; /* 0x10 - Window Attributes */
	63	#define POWAR_EN 0x80000000
	64	#define POWAR_IO_READ 0x00080000
	65	#define POWAR_MEM_READ 0x00040000
	66	#define POWAR_IO_WRITE 0x00008000
	67	#define POWAR_MEM_WRITE 0x00004000
	68	u32 res2[3];
	69	} pot_t;
	70
	71	typedef struct pci_inbound_window {
	72	u32 pitar; /* 0x00 - Address */
	73	u32 res1;
	74	u32 piwbar; /* 0x08 - Window Base Address */
	75	u32 piwbear; /* 0x0c - Window Base Address Extended */
	76	u32 piwar; /* 0x10 - Window Attributes */
	77	#define PIWAR_EN 0x80000000
	78	#define PIWAR_PF 0x20000000
	79	#define PIWAR_LOCAL 0x00f00000
	80	#define PIWAR_READ_SNOOP 0x00050000
	81	#define PIWAR_WRITE_SNOOP 0x00005000
	82	u32 res2[3];
	83	} pit_t;
	84
	85	/* PCI/PCI Express Registers */
	86	typedef struct ccsr_pci {
	87	u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */
	88	u32 cfg_data; /* 0x004 - PCI Configuration Data Register */
	89	u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */
	90	u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */
	91	u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */
	92	u32 config; /* 0x014 - PCIE CONFIG Register */
b6ccd2c9 PK	93	u32 int_status; /* 0x018 - PCIE interrupt status register */
b6ccd2c9 PK	94	char res2[4];
63cec581 ES	95	u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */
	96	u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
	97	u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
	98	u32 pm_command; /* 0x02c - PCIE PM Command register */
	99	char res4[3016]; /* (- #xbf8 #x30)3016 */
	100	u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
	101	u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
	102
	103	pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
b6ccd2c9 PK	104	u32 res5[24];
	105	pit_t pmit; /* 0xd00 - 0xd9c Inbound ATMU's MSI */
	106	u32 res6[24];
	107	pit_t pit[4]; /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
	108
63cec581 ES	109	#define PIT3 0
	110	#define PIT2 1
	111	#define PIT1 2
	112
	113	#if 0
	114	u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */
	115	u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
	116	char res5[8];
	117	u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */
	118	char res6[12];
	119	u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */
	120	u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
	121	u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */
	122	char res7[4];
	123	u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */
	124	char res8[12];
	125	u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */
	126	u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
	127	u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */
	128	char res9[4];
	129	u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */
	130	char res10[12];
	131	u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */
	132	u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
	133	u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */
	134	char res11[4];
	135	u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */
	136	char res12[12];
	137	u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */
	138	u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
	139	u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */
	140	char res13[4];
	141	u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */
	142	char res14[268];
	143	u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */
	144	char res15[4];
	145	u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */
	146	u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
	147	u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */
	148	char res16[12];
	149	u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */
	150	char res17[4];
	151	u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */
	152	u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
	153	u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */
	154	char res18[12];
	155	u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */
	156	char res19[4];
	157	u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */
	158	char res20[4];
	159	u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */
	160	char res21[12];
	161	#endif
	162	u32 pedr; /* 0xe00 - PCI Error Detect Register */
	163	u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */
	164	u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */
	165	u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */
	166	u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */
	167	/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */
	168	u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */
	169	u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */
	170	u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */
	171	u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */
	172	/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */
173	char res22[4];
174	u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */
175	u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
176	u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
177	u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
8ff3de61 KG	178	char res23[200];
8ff3de61 KG	179	u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
7b4e5844 ZRR	180	char res24[16];
	181	u32 pex_csr0; /* 0xf14 - PEX Control/Status register 0*/
	182	u32 pex_csr1; /* 0xf18 - PEX Control/Status register 1*/
	183	char res25[228];
63cec581	184	} ccsr_fsl_pci_t;
b6ccd2c9 PK	185	#define PCIE_CONFIG_PC 0x00020000
	186	#define PCIE_CONFIG_OB_CK 0x00002000
	187	#define PCIE_CONFIG_SAC 0x00000010
	188	#define PCIE_CONFIG_SP 0x80000002
	189	#define PCIE_CONFIG_SCC 0x80000001
63cec581	190
0d3d68b2	191	struct fsl_pci_info {
752bc335 TT	192	unsigned long regs;
	193	pci_addr_t mem_bus;
	194	phys_size_t mem_phys;
	195	pci_size_t mem_size;
	196	pci_addr_t io_bus;
	197	phys_size_t io_phys;
	198	pci_size_t io_size;
	199	enum law_trgt_if law;
	200	int pci_num;
0d3d68b2 PA	201	};
0d3d68b2 PA	202
213ac73e	203	void fsl_pci_init(struct pci_controller hose, struct fsl_pci_info pci_info);
0d3d68b2	204	int fsl_pci_init_port(struct fsl_pci_info *pci_info,
01471d53	205	struct pci_controller *hose, int busno);
a4aafcc9 KG	206	int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
	207	struct fsl_pci_info *pci_info);
	208	int fsl_pcie_init_board(int busno);
0d3d68b2	209
a8b3e90f PG	210	#define SET_STD_PCI_INFO(x, num) \
	211	{ \
	212	x.regs = CONFIG_SYS_PCI##num##_ADDR; \
	213	x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
	214	x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
	215	x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
	216	x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
	217	x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
	218	x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
752bc335	219	x.law = LAW_TRGT_IF_PCI_##num; \
a8b3e90f PG	220	x.pci_num = num; \
	221	}
	222
0d3d68b2 PA	223	#define SET_STD_PCIE_INFO(x, num) \
	224	{ \
	225	x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
	226	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
	227	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
	228	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
	229	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
	230	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
	231	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
752bc335	232	x.law = LAW_TRGT_IF_PCIE_##num; \
0d3d68b2 PA	233	x.pci_num = num; \
	234	}
	235
6525d51f	236	#define __FT_FSL_PCI_SETUP(blob, compat, num) \
3a0e3c27	237	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
6525d51f KG	238
6525d51f KG	239	#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
3a0e3c27	240	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
6525d51f	241
6525d51f	242	#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
6525d51f	243	#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
6525d51f	244
6525d51f	245	#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
6525d51f	246	#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
6525d51f	247	#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
6525d51f	248	#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
6525d51f	249
ae425c1e MM	250	#if !defined(CONFIG_PCI)
	251	#define FT_FSL_PCI_SETUP
	252	#elif defined(CONFIG_FSL_CORENET)
8f29084a	253	#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
6525d51f KG	254	#define FT_FSL_PCI_SETUP \
	255	FT_FSL_PCIE1_SETUP; \
	256	FT_FSL_PCIE2_SETUP; \
	257	FT_FSL_PCIE3_SETUP; \
	258	FT_FSL_PCIE4_SETUP;
a4aafcc9	259	#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
6525d51f KG	260	#elif defined(CONFIG_MPC85xx)
6525d51f KG	261	#define FSL_PCI_COMPAT "fsl,mpc8540-pci"
8f29084a KG	262	#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
	263	#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
	264	#else
6525d51f	265	#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
8f29084a	266	#endif
6525d51f KG	267	#define FT_FSL_PCI_SETUP \
	268	FT_FSL_PCI1_SETUP; \
	269	FT_FSL_PCI2_SETUP; \
	270	FT_FSL_PCIE1_SETUP; \
	271	FT_FSL_PCIE2_SETUP; \
	272	FT_FSL_PCIE3_SETUP;
a4aafcc9 KG	273	#define FT_FSL_PCIE_SETUP \
	274	FT_FSL_PCIE1_SETUP; \
	275	FT_FSL_PCIE2_SETUP; \
	276	FT_FSL_PCIE3_SETUP;
6525d51f KG	277	#elif defined(CONFIG_MPC86xx)
	278	#define FSL_PCI_COMPAT "fsl,mpc8610-pci"
	279	#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
	280	#define FT_FSL_PCI_SETUP \
	281	FT_FSL_PCI1_SETUP; \
	282	FT_FSL_PCIE1_SETUP; \
	283	FT_FSL_PCIE2_SETUP;
	284	#else
	285	#error FT_FSL_PCI_SETUP not defined
	286	#endif
	287
	288
32049b40	289	#endif