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7065b7d4 RG |
1 | /* |
2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
7065b7d4 RG |
5 | */ |
6 | ||
7 | #ifndef __FSL_SECURE_BOOT_H | |
8 | #define __FSL_SECURE_BOOT_H | |
e04916a7 | 9 | #include <asm/config_mpc85xx.h> |
10 | ||
11 | #ifdef CONFIG_SECURE_BOOT | |
bdc22074 AB |
12 | |
13 | #ifndef CONFIG_FIT_SIGNATURE | |
14 | #define CONFIG_CHAIN_OF_TRUST | |
e04916a7 | 15 | #endif |
7065b7d4 | 16 | |
7065b7d4 RG |
17 | #if defined(CONFIG_FSL_CORENET) |
18 | #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 | |
a202b9f8 | 19 | #elif defined(CONFIG_TARGET_BSC9132QDS) |
f978f7c2 | 20 | #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 |
ebccf255 | 21 | #elif defined(CONFIG_TARGET_C29XPCIE) |
b3f0f632 | 22 | #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 |
7065b7d4 RG |
23 | #else |
24 | #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 | |
25 | #endif | |
26 | #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 | |
27 | ||
d46a4a13 YS |
28 | #if defined(CONFIG_TARGET_B4860QDS) || \ |
29 | defined(CONFIG_TARGET_B4420QDS) || \ | |
9c21d06c | 30 | defined(CONFIG_TARGET_T4160QDS) || \ |
673c01c7 | 31 | defined(CONFIG_TARGET_T4240QDS) || \ |
80d26188 | 32 | defined(CONFIG_TARGET_T2080QDS) || \ |
86e0a313 | 33 | defined(CONFIG_TARGET_T2080RDB) || \ |
f4f66940 | 34 | defined(CONFIG_TARGET_T1040QDS) || \ |
78e56995 YS |
35 | defined(CONFIG_TARGET_T1040RDB) || \ |
36 | defined(CONFIG_TARGET_T1040D4RDB) || \ | |
37 | defined(CONFIG_TARGET_T1042RDB) || \ | |
38 | defined(CONFIG_TARGET_T1042D4RDB) || \ | |
39 | defined(CONFIG_TARGET_T1042RDB_PI) || \ | |
5ff3f41d | 40 | defined(CONFIG_ARCH_T1023) || \ |
e5d5f5a8 | 41 | defined(CONFIG_ARCH_T1024) |
aa36c84e | 42 | #ifndef CONFIG_SYS_RAMBOOT |
fb4a2409 | 43 | #define CONFIG_SYS_CPC_REINIT_F |
aa36c84e | 44 | #endif |
e04916a7 | 45 | #define CONFIG_KEY_REVOCATION |
fb4a2409 AB |
46 | #undef CONFIG_SYS_INIT_L3_ADDR |
47 | #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 | |
48 | #endif | |
49 | ||
467a40df AB |
50 | #if defined(CONFIG_RAMBOOT_PBL) |
51 | #undef CONFIG_SYS_INIT_L3_ADDR | |
aa36c84e SG |
52 | #ifdef CONFIG_SYS_INIT_L3_VADDR |
53 | #define CONFIG_SYS_INIT_L3_ADDR \ | |
54 | (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ | |
55 | 0xbff00000 | |
56 | #else | |
57 | #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 | |
58 | #endif | |
467a40df AB |
59 | #endif |
60 | ||
ebccf255 | 61 | #if defined(CONFIG_TARGET_C29XPCIE) |
e04916a7 | 62 | #define CONFIG_KEY_REVOCATION |
63 | #endif | |
64 | ||
5e5fdd2d | 65 | #if defined(CONFIG_ARCH_P3041) || \ |
e71372cb | 66 | defined(CONFIG_ARCH_P4080) || \ |
cefe11cd | 67 | defined(CONFIG_ARCH_P5020) || \ |
95390360 | 68 | defined(CONFIG_ARCH_P5040) || \ |
ce040c83 | 69 | defined(CONFIG_ARCH_P2041) |
e04916a7 | 70 | #define CONFIG_FSL_TRUST_ARCH_v1 |
71 | #endif | |
72 | ||
2ed948f4 | 73 | #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) |
e04916a7 | 74 | /* The key used for verification of next level images |
75 | * is picked up from an Extension Table which has | |
76 | * been verified by the ISBC (Internal Secure boot Code) | |
2ed948f4 AB |
77 | * in boot ROM of the SoC. |
78 | * The feature is only applicable in case of NOR boot and is | |
79 | * not applicable in case of RAMBOOT (NAND, SD, SPI). | |
e04916a7 | 80 | */ |
81 | #define CONFIG_FSL_ISBC_KEY_EXT | |
82 | #endif | |
bdc22074 AB |
83 | #endif /* #ifdef CONFIG_SECURE_BOOT */ |
84 | ||
85 | #ifdef CONFIG_CHAIN_OF_TRUST | |
b63f8a43 | 86 | #ifdef CONFIG_SPL_BUILD |
8f01397b SG |
87 | /* |
88 | * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init | |
89 | * due to space crunch on CPC and thus malloc will not work. | |
90 | */ | |
91 | #define CONFIG_SPL_PPAACT_ADDR 0x2e000000 | |
92 | #define CONFIG_SPL_SPAACT_ADDR 0x2f000000 | |
93 | #define CONFIG_SPL_JR0_LIODN_S 454 | |
94 | #define CONFIG_SPL_JR0_LIODN_NS 458 | |
95 | /* | |
96 | * Define the key hash for U-Boot here if public/private key pair used to | |
97 | * sign U-boot are different from the SRK hash put in the fuse | |
98 | * Example of defining KEY_HASH is | |
99 | * #define CONFIG_SPL_UBOOT_KEY_HASH \ | |
100 | * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" | |
101 | * else leave it defined as NULL | |
102 | */ | |
103 | ||
104 | #define CONFIG_SPL_UBOOT_KEY_HASH NULL | |
105 | #endif /* ifdef CONFIG_SPL_BUILD */ | |
106 | ||
bdc22074 AB |
107 | #define CONFIG_CMD_ESBC_VALIDATE |
108 | #define CONFIG_CMD_BLOB | |
109 | #define CONFIG_FSL_SEC_MON | |
110 | #define CONFIG_SHA_PROG_HW_ACCEL | |
bdc22074 AB |
111 | #define CONFIG_RSA_FREESCALE_EXP |
112 | ||
bdc22074 AB |
113 | #ifndef CONFIG_FSL_CAAM |
114 | #define CONFIG_FSL_CAAM | |
115 | #endif | |
e04916a7 | 116 | |
8f01397b SG |
117 | #ifndef CONFIG_SPL_BUILD |
118 | /* | |
119 | * fsl_setenv_chain_of_trust() must be called from | |
d0a6d7ce AB |
120 | * board_late_init() |
121 | */ | |
d0a6d7ce | 122 | |
5050f6f0 AB |
123 | /* If Boot Script is not on NOR and is required to be copied on RAM */ |
124 | #ifdef CONFIG_BOOTSCRIPT_COPY_RAM | |
125 | #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 | |
69d4b48c | 126 | #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 |
5050f6f0 AB |
127 | #define CONFIG_BS_HDR_SIZE 0x00002000 |
128 | #define CONFIG_BS_ADDR_RAM 0x00012000 | |
69d4b48c | 129 | #define CONFIG_BS_ADDR_DEVICE 0x00802000 |
5050f6f0 AB |
130 | #define CONFIG_BS_SIZE 0x00001000 |
131 | ||
132 | #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM | |
133 | #else | |
134 | ||
98cb0efd | 135 | /* The bootscript header address is different for B4860 because the NOR |
136 | * mapping is different on B4 due to reduced NOR size. | |
137 | */ | |
d46a4a13 | 138 | #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) |
98cb0efd | 139 | #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 |
140 | #elif defined(CONFIG_FSL_CORENET) | |
141 | #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 | |
a202b9f8 | 142 | #elif defined(CONFIG_TARGET_BSC9132QDS) |
98cb0efd | 143 | #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 |
ebccf255 | 144 | #elif defined(CONFIG_TARGET_C29XPCIE) |
98cb0efd | 145 | #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 |
146 | #else | |
147 | #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 | |
148 | #endif | |
149 | ||
bdc22074 | 150 | #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ |
98cb0efd | 151 | |
bdc22074 | 152 | #include <config_fsl_chain_trust.h> |
8f01397b | 153 | #endif /* #ifndef CONFIG_SPL_BUILD */ |
bdc22074 | 154 | #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ |
0d2cff2d | 155 | #endif |