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5e7abce9 SR |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5e7abce9 SR |
6 | */ |
7 | ||
8 | #ifndef _PPC440EPX_GRX_H_ | |
9 | #define _PPC440EPX_GRX_H_ | |
10 | ||
11 | #define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */ | |
12 | ||
13 | #define CONFIG_NAND_NDFC | |
14 | ||
5e7abce9 SR |
15 | /* |
16 | * Some SoC specific registers (not common for all 440 SoC's) | |
17 | */ | |
18 | ||
19 | /* Memory mapped registers */ | |
550650dd SR |
20 | #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ |
21 | ||
22 | #define SPI0_MODE (CONFIG_SYS_PERIPHERAL_BASE + 0x0090) | |
23 | ||
24 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) | |
25 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) | |
c96be63a SR |
26 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) |
27 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) | |
550650dd SR |
28 | |
29 | #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) | |
30 | #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) | |
5e7abce9 SR |
31 | |
32 | /* DCR */ | |
33 | #define CPM0_ER 0x00b0 | |
34 | #define CPM1_ER 0x00f0 | |
35 | #define PLB3A0_ACR 0x0077 | |
36 | #define PLB4A0_ACR 0x0081 | |
37 | #define PLB4A1_ACR 0x0089 | |
38 | #define OPB2PLB40_BCTRL 0x0350 | |
39 | #define P4P3BO0_CFG 0x0026 | |
40 | ||
41 | /* SDR */ | |
42 | #define SDR0_DDRCFG 0x00e0 | |
43 | #define SDR0_PCI0 0x0300 | |
44 | #define SDR0_SDSTP2 0x4001 | |
45 | #define SDR0_SDSTP3 0x4003 | |
46 | #define SDR0_EMAC0RXST 0x4301 | |
47 | #define SDR0_EMAC0TXST 0x4302 | |
48 | #define SDR0_CRYP0 0x4500 | |
49 | ||
50 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) | |
51 | #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) | |
52 | ||
53 | /* Pin Function Control Register 1 */ | |
54 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | |
55 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | |
56 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | |
57 | #define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select | |
58 | EMAC 0 */ | |
59 | #define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII | |
60 | bridge */ | |
61 | #define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII | |
62 | bridge */ | |
63 | #define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII | |
64 | bridge */ | |
65 | #define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII | |
66 | bridge */ | |
67 | #define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII | |
68 | bridge */ | |
69 | #define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII | |
70 | bridge */ | |
71 | #define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII | |
72 | bridge */ | |
73 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | |
74 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | |
75 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | |
76 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | |
77 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | |
78 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | |
79 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | |
80 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | |
81 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | |
82 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold | |
83 | Req Selection */ | |
84 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | |
85 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | |
86 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) | |
87 | Selection */ | |
88 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | |
89 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | |
90 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) | |
91 | Selection */ | |
92 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. | |
93 | Selected */ | |
94 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | |
95 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject | |
96 | Selection */ | |
97 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject | |
98 | Disable */ | |
99 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject | |
100 | Enable */ | |
101 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable | |
102 | Selection */ | |
103 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor | |
104 | Enable */ | |
105 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor | |
106 | Enable */ | |
107 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation | |
108 | Gated In */ | |
109 | ||
110 | #define SDR0_PFC2_SELECT_MASK 0xe0000000 /* Ethernet Pin select EMAC1 */ | |
111 | #define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ | |
112 | #define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ | |
113 | #define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ | |
114 | #define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ | |
115 | #define SDR0_PFC2_SELECT_CONFIG_4 0xa0000000 /* 2xRGMII using RGMII bridge */ | |
116 | #define SDR0_PFC2_SELECT_CONFIG_5 0xc0000000 /* 2xRTBI using RGMII bridge */ | |
117 | #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ | |
118 | ||
119 | #define SDR0_USB2D0CR 0x0320 | |
120 | #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC | |
121 | Master Selection */ | |
122 | #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection*/ | |
123 | #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ | |
124 | ||
125 | #define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface | |
126 | Selection */ | |
127 | #define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ | |
128 | #define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ | |
129 | ||
130 | #define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ | |
131 | #define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ | |
132 | #define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ | |
133 | ||
134 | /* USB2 Host Control Register */ | |
135 | #define SDR0_USB2H0CR 0x0340 | |
136 | #define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface*/ | |
137 | #define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ | |
138 | #define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ | |
139 | #define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length | |
140 | Adjustment */ | |
141 | /* USB2PHY0 Control Register */ | |
142 | #define SDR0_USB2PHY0CR 0x4103 | |
143 | #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 | |
144 | ||
145 | /* PHY UTMI interface connection */ | |
146 | #define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ | |
147 | #define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ | |
148 | ||
149 | #define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ | |
150 | #define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ | |
151 | #define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ | |
152 | ||
153 | /* VBus detect (Device mode only) */ | |
154 | #define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 | |
155 | /* Pull-up resistance on D+ is disabled */ | |
156 | #define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 | |
157 | /* Pull-up resistance on D+ is enabled */ | |
158 | #define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 | |
159 | ||
160 | /* PHY UTMI data width and clock select */ | |
161 | #define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 | |
162 | #define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ | |
163 | #define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ | |
164 | ||
165 | #define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ | |
166 | #define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ | |
167 | /* Loop back enabled (only test purposes) */ | |
168 | #define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 | |
169 | ||
170 | /* Force XO block on during a suspend */ | |
171 | #define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 | |
172 | #define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ | |
173 | /* PHY XO block is powered-off when all ports are suspended */ | |
174 | #define SDR0_USB2PHY0CR_XO_OFF 0x04000000 | |
175 | ||
176 | #define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ | |
177 | #define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ | |
178 | #define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only | |
179 | for full-speed operation */ | |
180 | ||
181 | #define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock | |
182 | source */ | |
183 | #define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal | |
184 | 48M clock as a reference */ | |
185 | #define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO | |
186 | block output as a reference */ | |
187 | ||
188 | #define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO | |
189 | block*/ | |
190 | #define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external | |
191 | clock */ | |
192 | #define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock | |
193 | from a crystal */ | |
194 | ||
195 | #define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ | |
196 | #define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq | |
197 | = 12 MHz */ | |
198 | #define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq | |
199 | = 48 MHz */ | |
200 | #define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq | |
201 | = 24 MHz */ | |
202 | ||
203 | /* USB2.0 Device */ | |
204 | /* | |
205 | * todo: check if this can be completely removed, only used in | |
206 | * cpu/ppc4xx/usbdev.c. And offsets are completely wrong. This could | |
207 | * never have actually worked. Best probably is to remove this | |
208 | * usbdev.c file completely (and these defines). | |
209 | */ | |
210 | #define USB2D0_BASE CONFIG_SYS_USB2D0_BASE | |
211 | ||
212 | #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) | |
213 | ||
214 | #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for | |
215 | Endpoint 0 plus IN Endpoints 1 to 3 */ | |
216 | #define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management | |
217 | register */ | |
218 | #define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address | |
219 | register */ | |
220 | #define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable | |
221 | register for USB2D0_INTRIN */ | |
222 | #define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for | |
223 | OUT Endpoints 1 to 3 */ | |
224 | #define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable | |
225 | register for USB2D0_INTRUSB */ | |
226 | #define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for | |
227 | common USB interrupts */ | |
228 | #define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable | |
229 | register for IntrOut */ | |
230 | #define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 | |
231 | test modes */ | |
232 | #define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for | |
233 | selecting the Endpoint status/control registers */ | |
234 | #define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */ | |
235 | #define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status | |
236 | register for Endpoint 0. (Index register set to select Endpoint 0) */ | |
237 | #define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status | |
238 | register for IN Endpoint. (Index register set to select Endpoints 13) */ | |
239 | #define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet | |
240 | size for IN Endpoint. (Index register set to select Endpoints 13) */ | |
241 | #define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status | |
242 | register for OUT Endpoint. (Index register set to select Endpoints 13) */ | |
243 | #define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet | |
244 | size for OUT Endpoint. (Index register set to select Endpoints 13) */ | |
245 | #define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received | |
246 | bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ | |
247 | #define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in | |
248 | OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ | |
249 | ||
250 | /* Miscealleneaous Function Reg. */ | |
251 | #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ | |
252 | #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 | |
253 | #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ | |
254 | #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 | |
255 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | |
256 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | |
257 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | |
258 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | |
259 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | |
260 | #define SDR0_MFR_ZM_ENCODE(n) ((((u32)(n)) & 0x3) << 24) | |
261 | #define SDR0_MFR_ZM_DECODE(n) ((((u32)(n)) << 24) & 0x3) | |
262 | #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ | |
263 | #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ | |
264 | #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ | |
265 | #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ | |
266 | #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ | |
267 | ||
268 | /* CUST0 Customer Configuration Register0 */ | |
269 | #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ | |
270 | #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ | |
271 | #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ | |
272 | #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ | |
273 | ||
274 | #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ | |
275 | #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ | |
276 | #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ | |
277 | ||
278 | #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ | |
279 | #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ | |
280 | #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ | |
281 | ||
282 | #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ | |
283 | #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24) | |
284 | #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF) | |
285 | ||
286 | #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ | |
287 | #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22) | |
288 | #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3) | |
289 | ||
290 | #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ | |
291 | #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ | |
292 | #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ | |
293 | ||
294 | #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ | |
295 | #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ | |
296 | #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ | |
297 | ||
298 | #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ | |
299 | #define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4) | |
300 | #define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF) | |
301 | ||
302 | #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ | |
303 | #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ | |
304 | #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ | |
305 | #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ | |
306 | #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ | |
307 | #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ | |
308 | #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ | |
309 | ||
310 | #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ | |
311 | #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ | |
312 | #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ | |
313 | #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ | |
314 | #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ | |
315 | transmitter 0 */ | |
316 | #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ | |
317 | transmitter 1 */ | |
318 | #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ | |
319 | #define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ | |
320 | #define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ | |
321 | #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ | |
322 | #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ | |
323 | #define SDR0_SRST0_PCI 0x00100000 /* PCI */ | |
324 | #define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ | |
325 | #define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ | |
326 | #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ | |
327 | #define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ | |
328 | #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ | |
329 | #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ | |
330 | #define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ | |
331 | #define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ | |
332 | #define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ | |
333 | #define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ | |
334 | #define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ | |
335 | #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ | |
336 | #define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ | |
337 | #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ | |
338 | #define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ | |
339 | #define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ | |
340 | #define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ | |
341 | #define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/ | |
342 | transmitter 2 */ | |
343 | #define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/ | |
344 | transmitter 3 */ | |
345 | ||
346 | #define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ | |
347 | #define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ | |
348 | #define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ | |
349 | #define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 | |
350 | #define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ | |
351 | #define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ | |
352 | #define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 | |
353 | USB 2.0 Host */ | |
354 | #define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to | |
355 | USB 2.0 Host */ | |
356 | #define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to | |
357 | USB 2.0 Host */ | |
358 | #define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ | |
359 | #define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2*/ | |
360 | #define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ | |
361 | #define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ | |
362 | #define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ | |
363 | #define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ | |
364 | #define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ | |
365 | #define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ | |
366 | #define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ | |
367 | #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ | |
368 | #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ | |
369 | ||
370 | #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ | |
371 | #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ | |
372 | #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ | |
373 | #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ | |
374 | #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ | |
375 | #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ | |
376 | #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ | |
377 | #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ | |
378 | #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ | |
379 | ||
380 | #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ | |
381 | #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ | |
382 | #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ | |
383 | #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ | |
384 | #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ | |
385 | #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ | |
386 | ||
387 | #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ | |
16263087 | 388 | #define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ |
5e7abce9 SR |
389 | #define PRADV_MASK 0x07000000 /* Primary Divisor A */ |
390 | #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ | |
391 | #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ | |
392 | ||
393 | /* Strap 1 Register */ | |
394 | #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ | |
395 | #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ | |
396 | #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ | |
397 | #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ | |
16263087 | 398 | #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ |
5e7abce9 SR |
399 | #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ |
400 | #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ | |
401 | #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ | |
402 | #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ | |
403 | #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ | |
404 | #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ | |
405 | #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ | |
406 | #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ | |
407 | #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ | |
408 | #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ | |
409 | #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ | |
410 | #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ | |
411 | #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ | |
412 | ||
413 | #define CPR0_ICFG_RLI_MASK 0x80000000 | |
414 | #define CPR0_ICFG_ICS_MASK 0x00000007 | |
415 | #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 | |
416 | #define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 | |
417 | #define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 | |
418 | #define CPR0_SPCID_SPCIDV0_DIV3 0x03000000 | |
419 | #define CPR0_SPCID_SPCIDV0_DIV4 0x00000000 | |
420 | #define CPR0_PERD_PERDV0_MASK 0x07000000 | |
421 | ||
422 | #define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => | |
423 | 0x0EF400000 */ | |
424 | ||
425 | /* PCI Master Local Configuration Registers */ | |
426 | #define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ | |
427 | #define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ | |
428 | #define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ | |
429 | #define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ | |
430 | #define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ | |
431 | #define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ | |
432 | #define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ | |
433 | #define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ | |
434 | #define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ | |
435 | #define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ | |
436 | #define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ | |
437 | #define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ | |
438 | ||
439 | /* PCI Target Local Configuration Registers */ | |
440 | #define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/ | |
441 | Attribute */ | |
442 | #define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ | |
443 | #define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/ | |
444 | Attribute */ | |
445 | #define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ | |
446 | ||
447 | /* 440EPx boot strap options */ | |
448 | #define BOOT_STRAP_OPTION_A 0x00000000 | |
449 | #define BOOT_STRAP_OPTION_B 0x00000001 | |
450 | #define BOOT_STRAP_OPTION_D 0x00000003 | |
451 | #define BOOT_STRAP_OPTION_E 0x00000004 | |
452 | ||
453 | #endif /* _PPC440EPX_GRX_H_ */ |