[people/ms/u-boot.git] / arch / powerpc / include / asm / ppc460sx.h

/*
 * (C) Copyright 2010
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _PPC460SX_H_
#define _PPC460SX_H_

#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */

/* Memory mapped registers */
#define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000 /* Internal Peripherals */

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)

#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)

#define SDR0_SRST0_DMC			0x00200000

#define PLLSYS0_FWD_DIV_A_MASK	0x000000f0	/* Fwd Div A */
#define PLLSYS0_FWD_DIV_B_MASK	0x0000000f	/* Fwd Div B */
#define PLLSYS0_FB_DIV_MASK	0x0000ff00	/* Feedback divisor */
#define PLLSYS0_OPB_DIV_MASK	0x0c000000	/* OPB Divisor */
#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000	/* PLB Early Clock Divisor */
#define PLLSYS0_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
#define PLLSYS0_SEL_MASK	0x18000000	/* 0 = PLL, 1 = PerClk */

#endif /* _PPC460SX_H_ */
Commit	Line	Data
5e7abce9 SR	1	/*
	2	* (C) Copyright 2010
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
5e7abce9 SR	6	*/
	7
	8	#ifndef _PPC460SX_H_
	9	#define _PPC460SX_H_
	10
	11	#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
	12
550650dd SR	13	/* Memory mapped registers */
	14	#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */
	15
	16	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
	17	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
	18
	19	#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
5e7abce9 SR	20
	21	#define SDR0_SRST0_DMC 0x00200000
	22
	23	#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
	24	#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
	25	#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
	26	#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
	27	#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
	28	#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
	29	#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
	30
	31	#endif /* _PPC460SX_H_ */