projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7ee2619c SR |
1 | /* |
| 2 | * (C) Copyright 2008 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 7ee2619c SR |
6 | */ |
| 7 | ||
| 8 | #ifndef _PPC4xx_EBC_H_ | |
| 9 | #define _PPC4xx_EBC_H_ | |
| 10 | ||
| 11 | /* | |
| 87800f72 EB |
12 | * Currently there are two register layout versions for the IBM EBC core |
| 13 | * used on 4xx PPC's. The following grouping lists the first layout. | |
| 14 | * Within this group there is a slight variation concerning the bit field | |
| 15 | * position of the EMPL and EMPH fields: | |
| 7ee2619c | 16 | */ |
| 3fb85889 | 17 | #if defined(CONFIG_405GP) || \ |
| 7ee2619c SR |
18 | defined(CONFIG_405EP) || \ |
| 19 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
| 20 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
| 21 | #define CONFIG_EBC_PPC4xx_IBM_VER1 | |
| 3fb85889 | 22 | #if defined(CONFIG_405GP) || \ |
| 87800f72 EB |
23 | defined(CONFIG_405EP) |
| 24 | #define EBC_CFG_EMPH_POS 8 | |
| 25 | #define EBC_CFG_EMPL_POS 6 | |
| 26 | #else | |
| 27 | #define EBC_CFG_EMPH_POS 6 | |
| 28 | #define EBC_CFG_EMPL_POS 8 | |
| 29 | #endif | |
| 7ee2619c SR |
30 | #endif |
| 31 | ||
| 43cbce69 SR |
32 | /* |
| 33 | * Define the max number of EBC banks (chip selects) | |
| 34 | */ | |
| 3fb85889 | 35 | #if defined(CONFIG_405GP) || \ |
| 43cbce69 SR |
36 | defined(CONFIG_405EZ) || \ |
| 37 | defined(CONFIG_440GP) || defined(CONFIG_440GX) | |
| 38 | #define EBC_NUM_BANKS 8 | |
| 39 | #endif | |
| 40 | ||
| 41 | #if defined(CONFIG_405EP) | |
| 42 | #define EBC_NUM_BANKS 5 | |
| 43 | #endif | |
| 44 | ||
| 45 | #if defined(CONFIG_405EX) || \ | |
| 46 | defined(CONFIG_460SX) | |
| 47 | #define EBC_NUM_BANKS 4 | |
| 48 | #endif | |
| 49 | ||
| 50 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
| 51 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
| 52 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
| 53 | #define EBC_NUM_BANKS 6 | |
| 54 | #endif | |
| 55 | ||
| 9ed3246e | 56 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
| 43cbce69 SR |
57 | #define EBC_NUM_BANKS 3 |
| 58 | #endif | |
| 59 | ||
| 7ee2619c | 60 | /* Bank Configuration Register */ |
| 43cbce69 SR |
61 | #define EBC_BXCR(n) (n) |
| 62 | #define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17)) | |
| 63 | ||
| 7ee2619c SR |
64 | #define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) |
| 65 | #define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK)) | |
| 66 | #define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) | |
| 67 | #define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) | |
| 68 | #define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) | |
| 69 | #define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) | |
| 70 | #define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) | |
| 71 | #define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) | |
| 72 | #define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) | |
| 73 | #define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) | |
| 74 | #define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) | |
| 75 | #define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) | |
| 76 | #define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) | |
| 77 | #define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) | |
| 78 | #define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) | |
| 79 | #define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) | |
| 80 | #define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) | |
| 81 | #define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) | |
| 82 | #define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) | |
| 83 | #if defined(CONFIG_EBC_PPC4xx_IBM_VER1) | |
| 84 | #define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x2) | |
| 85 | #else | |
| 86 | #define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) | |
| 87 | #endif | |
| 88 | ||
| 89 | /* Bank Access Parameter Register */ | |
| 90 | #define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) | |
| 91 | #define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) | |
| 92 | #define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF) | |
| 93 | #define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F) | |
| 94 | #define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7) | |
| 95 | #define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) | |
| 96 | #define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) | |
| 97 | #define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) | |
| 98 | #define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) | |
| 99 | #define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) | |
| 100 | #define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) | |
| 101 | #define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) | |
| 102 | #define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3) | |
| 103 | #define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3) | |
| 104 | #define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3) | |
| 105 | #define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3) | |
| 106 | #define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7) | |
| 107 | #define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) | |
| 108 | #define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) | |
| 109 | #define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) | |
| 110 | #define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) | |
| 111 | #define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) | |
| 112 | #define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) | |
| 113 | #define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) | |
| 114 | #define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) | |
| 115 | ||
| 116 | /* Common fields in EBC0_CFG register */ | |
| 117 | #define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) | |
| 118 | #define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) | |
| 119 | #define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) | |
| 120 | #define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) | |
| 121 | #define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) | |
| 122 | #define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) | |
| 123 | #define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) | |
| 124 | #define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) | |
| 125 | #define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) | |
| 126 | #define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) | |
| 127 | #define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) | |
| 128 | #define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) | |
| 129 | #define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) | |
| 130 | #define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) | |
| 131 | #define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) | |
| 132 | #define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) | |
| 133 | #define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F) | |
| 134 | ||
| 135 | /* Now the two versions of the other bits */ | |
| 136 | #if defined(CONFIG_EBC_PPC4xx_IBM_VER1) | |
| 137 | #define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1) | |
| 138 | #define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0) | |
| 139 | #define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1) | |
| 87800f72 EB |
140 | #define EBC_CFG_EMPH_MASK PPC_REG_VAL(EBC_CFG_EMPH_POS, 0x3) |
| 141 | #define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \ | |
| 142 | (static_cast(u32, n)) & 0x3) | |
| 143 | #define EBC_CFG_EMPL_MASK PPC_REG_VAL(EBC_CFG_EMPL_POS, 0x3) | |
| 144 | #define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \ | |
| 145 | (static_cast(u32, n)) & 0x3) | |
| 7ee2619c SR |
146 | #define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1) |
| 147 | #define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0) | |
| 148 | #define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1) | |
| 149 | #define EBC_CFG_BPR_MASK PPC_REG_VAL(11, 0x3) | |
| 150 | #define EBC_CFG_BPR_1DW PPC_REG_VAL(11, 0x0) | |
| 151 | #define EBC_CFG_BPR_2DW PPC_REG_VAL(11, 0x1) | |
| 152 | #define EBC_CFG_BPR_4DW PPC_REG_VAL(11, 0x2) | |
| 153 | #define EBC_CFG_EMS_MASK PPC_REG_VAL(13, 0x3) | |
| 154 | #define EBC_CFG_EMS_8BIT PPC_REG_VAL(13, 0x0) | |
| 155 | #define EBC_CFG_EMS_16BIT PPC_REG_VAL(13, 0x1) | |
| 156 | #define EBC_CFG_EMS_32BIT PPC_REG_VAL(13, 0x2) | |
| 157 | #else | |
| 158 | #define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) | |
| 159 | #define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) | |
| 160 | #define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) | |
| 161 | #define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) | |
| 162 | #define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) | |
| 163 | #define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) | |
| 164 | #define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) | |
| 165 | #define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) | |
| 166 | #define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) | |
| 167 | #define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) | |
| 168 | #define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) | |
| 169 | #define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) | |
| 170 | #define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) | |
| 171 | #define EBC_CFG_OEO_HI PPC_REG_VAL(8, 0x0) | |
| 172 | #define EBC_CFG_OEO_PREVIOUS PPC_REG_VAL(8, 0x1) | |
| 173 | #define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) | |
| 174 | #define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) | |
| 175 | #define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) | |
| 176 | #define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) | |
| 177 | #define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) | |
| 178 | #define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) | |
| 179 | #define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) | |
| 180 | #define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) | |
| 181 | #endif | |
| 182 | ||
| 183 | #endif /* _PPC4xx_EBC_H_ */ |