projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| b14ca4b6 DM |
1 | |
| 2 | /* | |
| 1a459660 | 3 | * SPDX-License-Identifier: GPL-2.0+ |
| b14ca4b6 DM |
4 | */ |
| 5 | ||
| 6 | #ifndef _PPC4xx_ISRAM_H_ | |
| 7 | #define _PPC4xx_ISRAM_H_ | |
| 8 | ||
| 9 | /* | |
| 10 | * Internal SRAM | |
| 11 | */ | |
| 1b8fec13 TM |
12 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
| 13 | defined(CONFIG_APM821XX) | |
| b14ca4b6 DM |
14 | #define ISRAM0_DCR_BASE 0x380 |
| 15 | #else | |
| 16 | #define ISRAM0_DCR_BASE 0x020 | |
| 17 | #endif | |
| 18 | #define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ | |
| 19 | #define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ | |
| 20 | #define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ | |
| 21 | #define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ | |
| 22 | #define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ | |
| 23 | #define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ | |
| 24 | #define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ | |
| 25 | #define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ | |
| 26 | #define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ | |
| 27 | #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ | |
| 28 | #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ | |
| 29 | ||
| 1b8fec13 TM |
30 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
| 31 | defined(CONFIG_APM821XX) | |
| b14ca4b6 DM |
32 | #define ISRAM1_DCR_BASE 0x0B0 |
| 33 | #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ | |
| 34 | #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ | |
| 35 | #define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */ | |
| 36 | #define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */ | |
| 37 | #define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */ | |
| 38 | #define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */ | |
| 39 | #define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */ | |
| 40 | #define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */ | |
| 41 | #endif /* CONFIG_460EX || CONFIG_460GT */ | |
| 42 | ||
| 1b8fec13 TM |
43 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 44 | #define ISRAM1_SIZE 0x0984 /* OCM size 64k */ | |
| 45 | #elif defined(CONFIG_APM821XX) | |
| 46 | #define ISRAM1_SIZE 0x0784 /* OCM size 32k */ | |
| 47 | #endif | |
| 48 | ||
| b14ca4b6 DM |
49 | /* |
| 50 | * L2 Cache | |
| 51 | */ | |
| 52 | #if defined (CONFIG_440GX) || \ | |
| 53 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ | |
| 54 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ | |
| 1b8fec13 | 55 | defined(CONFIG_460SX) || defined(CONFIG_APM821XX) |
| b14ca4b6 DM |
56 | #define L2_CACHE_BASE 0x030 |
| 57 | #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ | |
| 58 | #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ | |
| 59 | #define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */ | |
| 60 | #define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */ | |
| 61 | #define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */ | |
| 62 | #define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ | |
| 63 | #define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ | |
| 64 | #define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ | |
| 65 | #endif /* CONFIG_440GX */ | |
| 66 | ||
| 67 | #endif /* _PPC4xx_ISRAM_H_ */ |