[people/ms/u-boot.git] / arch / powerpc / include / asm / ppc4xx-isram.h

/*
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _PPC4xx_ISRAM_H_
#define _PPC4xx_ISRAM_H_

/*
 * Internal SRAM
 */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define ISRAM0_DCR_BASE 0x380
#else
#define ISRAM0_DCR_BASE 0x020
#endif
#define ISRAM0_SB0CR	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
#define ISRAM0_SB1CR	(ISRAM0_DCR_BASE+0x01)	/* SRAM bank config 1*/
#define ISRAM0_SB2CR	(ISRAM0_DCR_BASE+0x02)	/* SRAM bank config 2*/
#define ISRAM0_SB3CR	(ISRAM0_DCR_BASE+0x03)	/* SRAM bank config 3*/
#define ISRAM0_BEAR	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
#define ISRAM0_BESR0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
#define ISRAM0_BESR1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
#define ISRAM0_PMEG	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
#define ISRAM0_CID	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
#define ISRAM0_REVID	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
#define ISRAM0_DPC	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define ISRAM1_DCR_BASE 0x0B0
#define ISRAM1_SB0CR	(ISRAM1_DCR_BASE+0x00)	/* SRAM1 bank config 0*/
#define ISRAM1_BEAR	(ISRAM1_DCR_BASE+0x04)	/* SRAM1 bus error addr reg */
#define ISRAM1_BESR0	(ISRAM1_DCR_BASE+0x05)	/* SRAM1 bus error status reg 0 */
#define ISRAM1_BESR1	(ISRAM1_DCR_BASE+0x06)	/* SRAM1 bus error status reg 1 */
#define ISRAM1_PMEG	(ISRAM1_DCR_BASE+0x07)	/* SRAM1 power management */
#define ISRAM1_CID	(ISRAM1_DCR_BASE+0x08)	/* SRAM1 bus core id reg */
#define ISRAM1_REVID	(ISRAM1_DCR_BASE+0x09)	/* SRAM1 bus revision id reg */
#define ISRAM1_DPC	(ISRAM1_DCR_BASE+0x0a)	/* SRAM1 data parity check reg */
#endif /* CONFIG_460EX || CONFIG_460GT */

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define ISRAM1_SIZE 0x0984 /* OCM size 64k */
#endif

/*
 * L2 Cache
 */
#if defined (CONFIG_440GX) || \
    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
    defined(CONFIG_460SX)
#define L2_CACHE_BASE	0x030
#define L2_CACHE_CFG	(L2_CACHE_BASE+0x00)	/* L2 Cache Config      */
#define L2_CACHE_CMD	(L2_CACHE_BASE+0x01)	/* L2 Cache Command     */
#define L2_CACHE_ADDR	(L2_CACHE_BASE+0x02)	/* L2 Cache Address     */
#define L2_CACHE_DATA	(L2_CACHE_BASE+0x03)	/* L2 Cache Data        */
#define L2_CACHE_STAT	(L2_CACHE_BASE+0x04)	/* L2 Cache Status      */
#define L2_CACHE_CVER	(L2_CACHE_BASE+0x05)	/* L2 Cache Revision ID */
#define L2_CACHE_SNP0	(L2_CACHE_BASE+0x06)	/* L2 Cache Snoop reg 0 */
#define L2_CACHE_SNP1	(L2_CACHE_BASE+0x07)	/* L2 Cache Snoop reg 1 */
#endif /* CONFIG_440GX */

#endif /* _PPC4xx_ISRAM_H_ */
Commit	Line	Data
b14ca4b6	1	/*
1a459660	2	* SPDX-License-Identifier: GPL-2.0+
b14ca4b6 DM	3	*/
	4
	5	#ifndef _PPC4xx_ISRAM_H_
	6	#define _PPC4xx_ISRAM_H_
	7
	8	/*
	9	* Internal SRAM
	10	*/
9ed3246e	11	#if defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
b14ca4b6 DM	12	#define ISRAM0_DCR_BASE 0x380
	13	#else
	14	#define ISRAM0_DCR_BASE 0x020
	15	#endif
	16	#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
	17	#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
	18	#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
	19	#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
	20	#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
	21	#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
	22	#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
	23	#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
	24	#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
	25	#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
	26	#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
	27
9ed3246e	28	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
b14ca4b6 DM	29	#define ISRAM1_DCR_BASE 0x0B0
	30	#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
	31	#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
	32	#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */
	33	#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */
	34	#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */
	35	#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */
	36	#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */
	37	#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */
	38	#endif /* CONFIG_460EX \|\| CONFIG_460GT */
	39
1b8fec13 TM	40	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
1b8fec13 TM	41	#define ISRAM1_SIZE 0x0984 /* OCM size 64k */
1b8fec13 TM	42	#endif
1b8fec13 TM	43
b14ca4b6 DM	44	/*
	45	* L2 Cache
	46	*/
	47	#if defined (CONFIG_440GX) \|\| \
	48	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE) \|\| \
	49	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
9ed3246e	50	defined(CONFIG_460SX)
b14ca4b6 DM	51	#define L2_CACHE_BASE 0x030
	52	#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
	53	#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
	54	#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */
	55	#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */
	56	#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */
	57	#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
	58	#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
	59	#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
	60	#endif /* CONFIG_440GX */
	61
	62	#endif /* _PPC4xx_ISRAM_H_ */