[people/ms/u-boot.git] / arch / powerpc / include / asm / ppc4xx-mal.h

/* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
/*----------------------------------------------------------------------------+
|   This source code is dual-licensed.  You may use it under the terms of the
|   GNU General Public License version 2, or under the license below.
|
|	This source code has been made available to you by IBM on an AS-IS
|	basis.	Anyone receiving this source is licensed under IBM
|	copyrights to use it in any way he or she deems fit, including
|	copying it, modifying it, compiling it, and redistributing it either
|	with or without modifications.	No license under IBM patents or
|	patent applications is to be implied by the copyright license.
|
|	Any user of this software should understand that IBM cannot provide
|	technical support for this software and will not be responsible for
|	any consequences resulting from the use of this software.
|
|	Any person who transfers this source code or any derivative work
|	must include the IBM copyright notice, this paragraph, and the
|	preceding two paragraphs in the transferred software.
|
|	COPYRIGHT   I B M   CORPORATION 1999
|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
|
|  File Name:	mal.h
|
|  Function:	Header file for the MAL (MADMAL) macro on the 405GP.
|
|  Author:	Mark Wisner
|
|  Change Activity-
|
|  Date	       Description of Change					   BY
|  ---------   ---------------------					   ---
|  29-Apr-99   Created							   MKW
|
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
|  17-Nov-03  Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|	      Added register bit definitions to support multiple channels
+----------------------------------------------------------------------------*/
#ifndef _mal_h_
#define _mal_h_

#if !defined(MAL_DCR_BASE)
#define MAL_DCR_BASE	0x180
#endif
#define MAL0_CFG	(MAL_DCR_BASE + 0x00)	/* MAL Config reg	*/
#define MAL0_ESR	(MAL_DCR_BASE + 0x01)	/* Error Status (Read/Clear) */
#define MAL0_IER	(MAL_DCR_BASE + 0x02)	/* Interrupt enable */
#define MAL0_TXCASR	(MAL_DCR_BASE + 0x04)	/* TX Channel active (set) */
#define MAL0_TXCARR	(MAL_DCR_BASE + 0x05)	/* TX Channel active (reset) */
#define MAL0_TXEOBISR	(MAL_DCR_BASE + 0x06)	/* TX End of buffer int status*/
#define MAL0_TXDEIR	(MAL_DCR_BASE + 0x07)	/* TX Descr. Error Int */
#define MAL0_TXBADDR	(MAL_DCR_BASE + 0x09)	/* TX descriptor base addr*/
#define MAL0_RXCASR	(MAL_DCR_BASE + 0x10)	/* RX Channel active (set) */
#define MAL0_RXCARR	(MAL_DCR_BASE + 0x11)	/* RX Channel active (reset) */
#define MAL0_RXEOBISR	(MAL_DCR_BASE + 0x12)	/* RX End of buffer int status*/
#define MAL0_RXDEIR	(MAL_DCR_BASE + 0x13)	/* RX Descr. Error Int */
#define MAL0_RXBADDR	(MAL_DCR_BASE + 0x15)	/* RX descriptor base addr */
#define MAL0_TXCTP0R	(MAL_DCR_BASE + 0x20)	/* TX 0 Channel table pointer */
#define MAL0_TXCTP1R	(MAL_DCR_BASE + 0x21)	/* TX 1 Channel table pointer */
#define MAL0_TXCTP2R	(MAL_DCR_BASE + 0x22)	/* TX 2 Channel table pointer */
#define MAL0_TXCTP3R	(MAL_DCR_BASE + 0x23)	/* TX 3 Channel table pointer */
#define MAL0_RXCTP0R	(MAL_DCR_BASE + 0x40)	/* RX 0 Channel table pointer */
#define MAL0_RXCTP1R	(MAL_DCR_BASE + 0x41)	/* RX 1 Channel table pointer */
#define MAL0_RCBS0	(MAL_DCR_BASE + 0x60)	/* RX 0 Channel buffer size */
#define MAL0_RCBS1	(MAL_DCR_BASE + 0x61)	/* RX 1 Channel buffer size */
#if defined(CONFIG_440GX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define MAL0_RXCTP2R	(MAL_DCR_BASE + 0x42)	/* RX 2 Channel table pointer */
#define MAL0_RXCTP3R	(MAL_DCR_BASE + 0x43)	/* RX 3 Channel table pointer */
#define MAL0_RXCTP8R	(MAL_DCR_BASE + 0x48)	/* RX 8 Channel table pointer */
#define MAL0_RXCTP16R	(MAL_DCR_BASE + 0x50)	/* RX 16 Channel table pointer*/
#define MAL0_RXCTP24R	(MAL_DCR_BASE + 0x58)	/* RX 24 Channel table pointer*/
#define MAL0_RCBS2	(MAL_DCR_BASE + 0x62)	/* RX 2 Channel buffer size */
#define MAL0_RCBS3	(MAL_DCR_BASE + 0x63)	/* RX 3 Channel buffer size */
#define MAL0_RCBS8	(MAL_DCR_BASE + 0x68)	/* RX 8 Channel buffer size */
#define MAL0_RCBS16	(MAL_DCR_BASE + 0x70)	/* RX 16 Channel buffer size */
#define MAL0_RCBS24	(MAL_DCR_BASE + 0x78)	/* RX 24 Channel buffer size */
#endif /* CONFIG_440GX */

/* MADMAL transmit and receive status/control bits  */
/* for COMMAC bits, refer to the COMMAC header file */

#define MAL_TX_CTRL_READY 0x8000
#define MAL_TX_CTRL_WRAP  0x4000
#define MAL_TX_CTRL_CM	  0x2000
#define MAL_TX_CTRL_LAST  0x1000
#define MAL_TX_CTRL_INTR  0x0400

#define MAL_RX_CTRL_EMPTY 0x8000
#define MAL_RX_CTRL_WRAP  0x4000
#define MAL_RX_CTRL_CM	  0x2000
#define MAL_RX_CTRL_LAST  0x1000
#define MAL_RX_CTRL_FIRST 0x0800
#define MAL_RX_CTRL_INTR  0x0400

      /* Configuration Reg  */
#define MAL_CR_MMSR	  0x80000000
#define MAL_CR_PLBP_1	  0x00400000   /* lowsest is 00 */
#define MAL_CR_PLBP_2	  0x00800000
#define MAL_CR_PLBP_3	  0x00C00000   /* highest	*/
#define MAL_CR_GA	  0x00200000
#define MAL_CR_OA	  0x00100000
#define MAL_CR_PLBLE	  0x00080000
#define MAL_CR_PLBLT_1	0x00040000
#define MAL_CR_PLBLT_2	0x00020000
#define MAL_CR_PLBLT_3	0x00010000
#define MAL_CR_PLBLT_4	0x00008000
#define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
#define MAL_CR_PLBB	  0x00004000
#define MAL_CR_OPBBL	  0x00000080
#define MAL_CR_EOPIE	  0x00000004
#define MAL_CR_LEA	  0x00000002
#define MAL_CR_MSD	  0x00000001

    /* Error Status Reg	   */
#define MAL_ESR_EVB	  0x80000000
#define MAL_ESR_CID	  0x40000000
#define MAL_ESR_DE	  0x00100000
#define MAL_ESR_ONE	  0x00080000
#define MAL_ESR_OTE	  0x00040000
#define MAL_ESR_OSE	  0x00020000
#define MAL_ESR_PEIN	  0x00010000
      /* same bit position as the IER */
      /* VV			 VV   */
#define MAL_ESR_DEI	  0x00000010
#define MAL_ESR_ONEI	  0x00000008
#define MAL_ESR_OTEI	  0x00000004
#define MAL_ESR_OSEI	  0x00000002
#define MAL_ESR_PBEI	  0x00000001
      /* ^^			 ^^   */
      /* Mal IER		      */
#if defined(CONFIG_440SPE) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
    defined(CONFIG_405EX)
#define MAL_IER_PT	  0x00000080
#define MAL_IER_PRE	  0x00000040
#define MAL_IER_PWE	  0x00000020
#define MAL_IER_DE	  0x00000010
#define MAL_IER_OTE	  0x00000004
#define MAL_IER_OE	  0x00000002
#define MAL_IER_PE	  0x00000001
#else
#define MAL_IER_DE	  0x00000010
#define MAL_IER_NE	  0x00000008
#define MAL_IER_TE	  0x00000004
#define MAL_IER_OPBE	  0x00000002
#define MAL_IER_PLBE	  0x00000001
#endif

/* MAL Channel Active Set and Reset Registers */
#define MAL_TXRX_CASR	(0x80000000)

#define MAL_TXRX_CASR_V(__x)  (__x)  /* Channel 0 shifts 0, channel 1 shifts 1, etc */


/* MAL Buffer Descriptor structure */
typedef struct {
  short	 ctrl;		    /* MAL / Commac status control bits */
  short	 data_len;	    /* Max length is 4K-1 (12 bits)	*/
  char	*data_ptr;	    /* pointer to actual data buffer	*/
} mal_desc_t;

#endif
Commit	Line	Data
4a5b6a35 WD	1	/* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
4a5b6a35 WD	2	/*----------------------------------------------------------------------------+
31773496 JB	3	\| This source code is dual-licensed. You may use it under the terms of the
31773496 JB	4	\| GNU General Public License version 2, or under the license below.
4a5b6a35	5	\|
ba56f625 WD	6	\| This source code has been made available to you by IBM on an AS-IS
	7	\| basis. Anyone receiving this source is licensed under IBM
	8	\| copyrights to use it in any way he or she deems fit, including
	9	\| copying it, modifying it, compiling it, and redistributing it either
	10	\| with or without modifications. No license under IBM patents or
	11	\| patent applications is to be implied by the copyright license.
4a5b6a35	12	\|
ba56f625 WD	13	\| Any user of this software should understand that IBM cannot provide
	14	\| technical support for this software and will not be responsible for
	15	\| any consequences resulting from the use of this software.
4a5b6a35	16	\|
ba56f625 WD	17	\| Any person who transfers this source code or any derivative work
	18	\| must include the IBM copyright notice, this paragraph, and the
	19	\| preceding two paragraphs in the transferred software.
4a5b6a35	20	\|
ba56f625 WD	21	\| COPYRIGHT I B M CORPORATION 1999
ba56f625 WD	22	\| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
4a5b6a35 WD	23	+----------------------------------------------------------------------------*/
	24	/*----------------------------------------------------------------------------+
	25	\|
ba56f625	26	\| File Name: mal.h
4a5b6a35	27	\|
ba56f625	28	\| Function: Header file for the MAL (MADMAL) macro on the 405GP.
4a5b6a35	29	\|
ba56f625	30	\| Author: Mark Wisner
4a5b6a35 WD	31	\|
	32	\| Change Activity-
	33	\|
ba56f625 WD	34	\| Date Description of Change BY
	35	\| --------- --------------------- ---
	36	\| 29-Apr-99 Created MKW
4a5b6a35 WD	37	\|
4a5b6a35 WD	38	+----------------------------------------------------------------------------*/
ba56f625 WD	39	/*----------------------------------------------------------------------------+
	40	\| 17-Nov-03 Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
	41	\| Added register bit definitions to support multiple channels
	42	+----------------------------------------------------------------------------*/
4a5b6a35 WD	43	#ifndef _mal_h_
4a5b6a35 WD	44	#define _mal_h_
5e7abce9 SR	45
	46	#if !defined(MAL_DCR_BASE)
	47	#define MAL_DCR_BASE 0x180
	48	#endif
	49	#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */
	50	#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */
	51	#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
	52	#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
	53	#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
	54	#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/
	55	#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */
	56	#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/
	57	#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
	58	#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
	59	#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/
	60	#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */
	61	#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */
	62	#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */
	63	#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */
	64	#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */
	65	#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */
	66	#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */
	67	#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */
	68	#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */
	69	#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */
	70	#if defined(CONFIG_440GX) \|\| \
	71	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	72	#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */
	73	#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */
	74	#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */
	75	#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/
	76	#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/
	77	#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */
	78	#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */
	79	#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */
	80	#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
	81	#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
	82	#endif /* CONFIG_440GX */
	83
4a5b6a35 WD	84	/* MADMAL transmit and receive status/control bits */
	85	/* for COMMAC bits, refer to the COMMAC header file */
	86
	87	#define MAL_TX_CTRL_READY 0x8000
	88	#define MAL_TX_CTRL_WRAP 0x4000
ba56f625	89	#define MAL_TX_CTRL_CM 0x2000
4a5b6a35 WD	90	#define MAL_TX_CTRL_LAST 0x1000
	91	#define MAL_TX_CTRL_INTR 0x0400
	92
	93	#define MAL_RX_CTRL_EMPTY 0x8000
	94	#define MAL_RX_CTRL_WRAP 0x4000
	95	#define MAL_RX_CTRL_CM 0x2000
	96	#define MAL_RX_CTRL_LAST 0x1000
	97	#define MAL_RX_CTRL_FIRST 0x0800
	98	#define MAL_RX_CTRL_INTR 0x0400
	99
	100	/* Configuration Reg */
	101	#define MAL_CR_MMSR 0x80000000
	102	#define MAL_CR_PLBP_1 0x00400000 /* lowsest is 00 */
	103	#define MAL_CR_PLBP_2 0x00800000
ba56f625	104	#define MAL_CR_PLBP_3 0x00C00000 /* highest */
4a5b6a35 WD	105	#define MAL_CR_GA 0x00200000
	106	#define MAL_CR_OA 0x00100000
	107	#define MAL_CR_PLBLE 0x00080000
ba56f625 WD	108	#define MAL_CR_PLBLT_1 0x00040000
	109	#define MAL_CR_PLBLT_2 0x00020000
	110	#define MAL_CR_PLBLT_3 0x00010000
	111	#define MAL_CR_PLBLT_4 0x00008000
4a5b6a35 WD	112	#define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
	113	#define MAL_CR_PLBB 0x00004000
	114	#define MAL_CR_OPBBL 0x00000080
	115	#define MAL_CR_EOPIE 0x00000004
	116	#define MAL_CR_LEA 0x00000002
	117	#define MAL_CR_MSD 0x00000001
	118
ba56f625	119	/* Error Status Reg */
4a5b6a35 WD	120	#define MAL_ESR_EVB 0x80000000
	121	#define MAL_ESR_CID 0x40000000
	122	#define MAL_ESR_DE 0x00100000
	123	#define MAL_ESR_ONE 0x00080000
	124	#define MAL_ESR_OTE 0x00040000
	125	#define MAL_ESR_OSE 0x00020000
	126	#define MAL_ESR_PEIN 0x00010000
	127	/* same bit position as the IER */
ba56f625	128	/* VV VV */
4a5b6a35 WD	129	#define MAL_ESR_DEI 0x00000010
	130	#define MAL_ESR_ONEI 0x00000008
	131	#define MAL_ESR_OTEI 0x00000004
	132	#define MAL_ESR_OSEI 0x00000002
	133	#define MAL_ESR_PBEI 0x00000001
ba56f625 WD	134	/* ^^ ^^ */
ba56f625 WD	135	/* Mal IER */
dbbd1257 SR	136	#if defined(CONFIG_440SPE) \|\| \
dbbd1257 SR	137	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
999ecd5a	138	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
dbbd1257	139	defined(CONFIG_405EX)
6c5879f3 MB	140	#define MAL_IER_PT 0x00000080
	141	#define MAL_IER_PRE 0x00000040
	142	#define MAL_IER_PWE 0x00000020
	143	#define MAL_IER_DE 0x00000010
	144	#define MAL_IER_OTE 0x00000004
	145	#define MAL_IER_OE 0x00000002
	146	#define MAL_IER_PE 0x00000001
	147	#else
4a5b6a35 WD	148	#define MAL_IER_DE 0x00000010
	149	#define MAL_IER_NE 0x00000008
	150	#define MAL_IER_TE 0x00000004
	151	#define MAL_IER_OPBE 0x00000002
	152	#define MAL_IER_PLBE 0x00000001
6c5879f3	153	#endif
4a5b6a35	154
ba56f625 WD	155	/* MAL Channel Active Set and Reset Registers */
	156	#define MAL_TXRX_CASR (0x80000000)
	157
	158	#define MAL_TXRX_CASR_V(__x) (__x) /* Channel 0 shifts 0, channel 1 shifts 1, etc */
	159
4a5b6a35 WD	160
	161	/* MAL Buffer Descriptor structure */
	162	typedef struct {
ba56f625 WD	163	short ctrl; /* MAL / Commac status control bits */
	164	short data_len; /* Max length is 4K-1 (12 bits) */
	165	char data_ptr; / pointer to actual data buffer */
4a5b6a35 WD	166	} mal_desc_t;
	167
	168	#endif