projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c609719b | 1 | /* |
| 4fb25a3d SR |
2 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 3 | * | |
| 952e7760 | 4 | * (C) Copyright 2008-2009 |
| 4fb25a3d SR |
5 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 6 | * | |
| 3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| c609719b WD |
8 | */ |
| 9 | ||
| 4fb25a3d SR |
10 | #ifndef _PPC4xx_UIC_H_ |
| 11 | #define _PPC4xx_UIC_H_ | |
| c609719b | 12 | |
| d1631fe1 SR |
13 | /* |
| 14 | * Define the number of UIC's | |
| 15 | */ | |
| 5de85140 | 16 | #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ |
| 3a82113e | 17 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
| 9ed3246e | 18 | defined(CONFIG_460SX) |
| d1631fe1 | 19 | #define UIC_MAX 4 |
| 5de85140 | 20 | #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
| d1631fe1 SR |
21 | defined(CONFIG_405EX) |
| 22 | #define UIC_MAX 3 | |
| 23 | #elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ | |
| 24 | defined(CONFIG_440EP) || defined(CONFIG_440GR) | |
| 25 | #define UIC_MAX 2 | |
| 26 | #else | |
| 27 | #define UIC_MAX 1 | |
| 28 | #endif | |
| 887e2ec9 | 29 | |
| 952e7760 | 30 | #define IRQ_MAX (UIC_MAX * 32) |
| d865fd09 | 31 | |
| d1631fe1 SR |
32 | /* |
| 33 | * UIC register | |
| 34 | */ | |
| 35 | #define UIC_SR 0x0 /* UIC status */ | |
| 36 | #define UIC_ER 0x2 /* UIC enable */ | |
| 37 | #define UIC_CR 0x3 /* UIC critical */ | |
| 38 | #define UIC_PR 0x4 /* UIC polarity */ | |
| 39 | #define UIC_TR 0x5 /* UIC triggering */ | |
| 40 | #define UIC_MSR 0x6 /* UIC masked status */ | |
| 41 | #define UIC_VR 0x7 /* UIC vector */ | |
| 42 | #define UIC_VCR 0x8 /* UIC vector configuration */ | |
| 43 | ||
| 5de85140 SR |
44 | /* |
| 45 | * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's | |
| 46 | * are cascaded on. With this trick we can use the common UIC code for 440GX | |
| 47 | * too. | |
| 48 | */ | |
| 49 | #if defined(CONFIG_440GX) | |
| 50 | #define UIC0_DCR_BASE 0x200 | |
| 51 | #define UIC1_DCR_BASE 0xc0 | |
| 52 | #define UIC2_DCR_BASE 0xd0 | |
| 53 | #define UIC3_DCR_BASE 0x210 | |
| 54 | #else | |
| d1631fe1 | 55 | #define UIC0_DCR_BASE 0xc0 |
| 5de85140 SR |
56 | #define UIC1_DCR_BASE 0xd0 |
| 57 | #define UIC2_DCR_BASE 0xe0 | |
| 58 | #define UIC3_DCR_BASE 0xf0 | |
| 59 | #endif | |
| 60 | ||
| 952e7760 SR |
61 | #define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */ |
| 62 | #define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */ | |
| 63 | #define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */ | |
| 64 | #define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ | |
| 65 | #define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ | |
| 66 | #define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ | |
| 67 | #define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */ | |
| 68 | #define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ | |
| d1631fe1 | 69 | |
| 952e7760 SR |
70 | #define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */ |
| 71 | #define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */ | |
| 72 | #define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */ | |
| 73 | #define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ | |
| 74 | #define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ | |
| 75 | #define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ | |
| 76 | #define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */ | |
| 77 | #define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ | |
| d1631fe1 | 78 | |
| 952e7760 SR |
79 | #define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ |
| 80 | #define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */ | |
| 81 | #define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */ | |
| 82 | #define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ | |
| 83 | #define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ | |
| 84 | #define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ | |
| 85 | #define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */ | |
| 86 | #define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ | |
| d1631fe1 | 87 | |
| 952e7760 SR |
88 | #define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ |
| 89 | #define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */ | |
| 90 | #define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */ | |
| 91 | #define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ | |
| 92 | #define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ | |
| 93 | #define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ | |
| 94 | #define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */ | |
| 95 | #define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ | |
| 887e2ec9 | 96 | |
| d1631fe1 SR |
97 | /* |
| 98 | * Now the interrupt vector definitions. They are different for most of | |
| 99 | * the 4xx variants, so we need some more #ifdef's here. No mask | |
| 100 | * definitions anymore here. For this please use the UIC_MASK macro below. | |
| 101 | * | |
| 102 | * Note: Please only define the interrupts really used in U-Boot here. | |
| 103 | * Those are the cascading and EMAC/MAL related interrupt. | |
| 104 | */ | |
| 887e2ec9 | 105 | |
| d1631fe1 SR |
106 | #if defined(CONFIG_405EP) || defined(CONFIG_405GP) |
| 107 | #define VECNUM_MAL_SERR 10 | |
| 108 | #define VECNUM_MAL_TXEOB 11 | |
| 109 | #define VECNUM_MAL_RXEOB 12 | |
| 110 | #define VECNUM_MAL_TXDE 13 | |
| 111 | #define VECNUM_MAL_RXDE 14 | |
| 112 | #define VECNUM_ETH0 15 | |
| 113 | #define VECNUM_ETH1_OFFS 2 | |
| 114 | #define VECNUM_EIRQ6 29 | |
| 115 | #endif /* defined(CONFIG_405EP) */ | |
| 999ecd5a | 116 | |
| d1631fe1 SR |
117 | #if defined(CONFIG_405EZ) |
| 118 | #define VECNUM_USBDEV 15 | |
| 119 | #define VECNUM_ETH0 16 | |
| 120 | #define VECNUM_MAL_SERR 18 | |
| 121 | #define VECNUM_MAL_TXDE 18 | |
| 122 | #define VECNUM_MAL_RXDE 18 | |
| 123 | #define VECNUM_MAL_TXEOB 19 | |
| 124 | #define VECNUM_MAL_RXEOB 21 | |
| 125 | #endif /* CONFIG_405EX */ | |
| 126 | ||
| 127 | #if defined(CONFIG_405EX) | |
| 999ecd5a | 128 | /* UIC 0 */ |
| d1631fe1 SR |
129 | #define VECNUM_MAL_TXEOB 10 |
| 130 | #define VECNUM_MAL_RXEOB 11 | |
| 131 | #define VECNUM_ETH0 24 | |
| 132 | #define VECNUM_ETH1_OFFS 1 | |
| 133 | #define VECNUM_UIC2NCI 28 | |
| 134 | #define VECNUM_UIC2CI 29 | |
| 135 | #define VECNUM_UIC1NCI 30 | |
| 136 | #define VECNUM_UIC1CI 31 | |
| 999ecd5a SR |
137 | |
| 138 | /* UIC 1 */ | |
| d1631fe1 SR |
139 | #define VECNUM_MAL_SERR (32 + 0) |
| 140 | #define VECNUM_MAL_TXDE (32 + 1) | |
| 141 | #define VECNUM_MAL_RXDE (32 + 2) | |
| 142 | #endif /* CONFIG_405EX */ | |
| 887e2ec9 | 143 | |
| d1631fe1 SR |
144 | #if defined(CONFIG_440GP) || \ |
| 145 | defined(CONFIG_440EP) || defined(CONFIG_440GR) | |
| 6c5879f3 | 146 | /* UIC 0 */ |
| d1631fe1 SR |
147 | #define VECNUM_MAL_TXEOB 10 |
| 148 | #define VECNUM_MAL_RXEOB 11 | |
| 149 | #define VECNUM_UIC1NCI 30 | |
| 150 | #define VECNUM_UIC1CI 31 | |
| 6c5879f3 MB |
151 | |
| 152 | /* UIC 1 */ | |
| d1631fe1 SR |
153 | #define VECNUM_MAL_SERR (32 + 0) |
| 154 | #define VECNUM_MAL_TXDE (32 + 1) | |
| 155 | #define VECNUM_MAL_RXDE (32 + 2) | |
| 156 | #define VECNUM_USBDEV (32 + 23) | |
| 157 | #define VECNUM_ETH0 (32 + 28) | |
| 158 | #define VECNUM_ETH1_OFFS 2 | |
| 159 | #endif /* CONFIG_440GP */ | |
| 160 | ||
| 161 | #if defined(CONFIG_440GX) | |
| 5de85140 SR |
162 | /* UICB 0 (440GX only) */ |
| 163 | /* | |
| 164 | * All those defines below are off-by-one, so that the common UIC code | |
| 165 | * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc. | |
| 166 | */ | |
| 167 | #define VECNUM_UIC1CI 0 | |
| 168 | #define VECNUM_UIC1NCI 1 | |
| 169 | #define VECNUM_UIC2CI 2 | |
| 170 | #define VECNUM_UIC2NCI 3 | |
| 171 | #define VECNUM_UIC3CI 4 | |
| 172 | #define VECNUM_UIC3NCI 5 | |
| 6e7fb6ea | 173 | |
| 5de85140 SR |
174 | /* UIC 0, used as UIC1 on 440GX because of UICB0 */ |
| 175 | #define VECNUM_MAL_TXEOB (32 + 10) | |
| 176 | #define VECNUM_MAL_RXEOB (32 + 11) | |
| d1631fe1 | 177 | |
| 5de85140 SR |
178 | /* UIC 1, used as UIC2 on 440GX because of UICB0 */ |
| 179 | #define VECNUM_MAL_SERR (64 + 0) | |
| 180 | #define VECNUM_MAL_TXDE (64 + 1) | |
| 181 | #define VECNUM_MAL_RXDE (64 + 2) | |
| 182 | #define VECNUM_ETH0 (64 + 28) | |
| 183 | #define VECNUM_ETH1_OFFS 2 | |
| d1631fe1 | 184 | #endif /* CONFIG_440GX */ |
| c609719b | 185 | |
| d1631fe1 | 186 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
| c609719b | 187 | /* UIC 0 */ |
| d1631fe1 SR |
188 | #define VECNUM_MAL_TXEOB 10 |
| 189 | #define VECNUM_MAL_RXEOB 11 | |
| 190 | #define VECNUM_USBDEV 20 | |
| 191 | #define VECNUM_ETH0 24 | |
| 192 | #define VECNUM_ETH1_OFFS 1 | |
| 193 | #define VECNUM_UIC2NCI 28 | |
| 194 | #define VECNUM_UIC2CI 29 | |
| 195 | #define VECNUM_UIC1NCI 30 | |
| 196 | #define VECNUM_UIC1CI 31 | |
| c609719b WD |
197 | |
| 198 | /* UIC 1 */ | |
| d1631fe1 SR |
199 | #define VECNUM_MAL_SERR (32 + 0) |
| 200 | #define VECNUM_MAL_TXDE (32 + 1) | |
| 201 | #define VECNUM_MAL_RXDE (32 + 2) | |
| e01bd218 | 202 | |
| d1631fe1 SR |
203 | /* UIC 2 */ |
| 204 | #define VECNUM_EIRQ2 (64 + 3) | |
| 205 | #endif /* CONFIG_440EPX */ | |
| e01bd218 | 206 | |
| d1631fe1 SR |
207 | #if defined(CONFIG_440SP) |
| 208 | /* UIC 0 */ | |
| 209 | #define VECNUM_UIC1NCI 30 | |
| 210 | #define VECNUM_UIC1CI 31 | |
| dbbd1257 | 211 | |
| d1631fe1 SR |
212 | /* UIC 1 */ |
| 213 | #define VECNUM_MAL_SERR (32 + 1) | |
| 214 | #define VECNUM_MAL_TXDE (32 + 2) | |
| 215 | #define VECNUM_MAL_RXDE (32 + 3) | |
| 216 | #define VECNUM_MAL_TXEOB (32 + 6) | |
| 217 | #define VECNUM_MAL_RXEOB (32 + 7) | |
| 218 | #define VECNUM_ETH0 (32 + 28) | |
| 219 | #endif /* CONFIG_440SP */ | |
| 220 | ||
| 221 | #if defined(CONFIG_440SPE) | |
| dbbd1257 | 222 | /* UIC 0 */ |
| d1631fe1 SR |
223 | #define VECNUM_UIC2NCI 10 |
| 224 | #define VECNUM_UIC2CI 11 | |
| 225 | #define VECNUM_UIC3NCI 16 | |
| 226 | #define VECNUM_UIC3CI 17 | |
| 227 | #define VECNUM_UIC1NCI 30 | |
| 228 | #define VECNUM_UIC1CI 31 | |
| dbbd1257 SR |
229 | |
| 230 | /* UIC 1 */ | |
| d1631fe1 SR |
231 | #define VECNUM_MAL_SERR (32 + 1) |
| 232 | #define VECNUM_MAL_TXDE (32 + 2) | |
| 233 | #define VECNUM_MAL_RXDE (32 + 3) | |
| 234 | #define VECNUM_MAL_TXEOB (32 + 6) | |
| 235 | #define VECNUM_MAL_RXEOB (32 + 7) | |
| 236 | #define VECNUM_ETH0 (32 + 28) | |
| 237 | #endif /* CONFIG_440SPE */ | |
| 238 | ||
| 9ed3246e | 239 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| d1631fe1 SR |
240 | /* UIC 0 */ |
| 241 | #define VECNUM_UIC2NCI 10 | |
| 242 | #define VECNUM_UIC2CI 11 | |
| 243 | #define VECNUM_UIC3NCI 16 | |
| 244 | #define VECNUM_UIC3CI 17 | |
| 245 | #define VECNUM_UIC1NCI 30 | |
| 246 | #define VECNUM_UIC1CI 31 | |
| dbbd1257 SR |
247 | |
| 248 | /* UIC 2 */ | |
| d1631fe1 SR |
249 | #define VECNUM_MAL_SERR (64 + 3) |
| 250 | #define VECNUM_MAL_TXDE (64 + 4) | |
| 251 | #define VECNUM_MAL_RXDE (64 + 5) | |
| 252 | #define VECNUM_MAL_TXEOB (64 + 6) | |
| 253 | #define VECNUM_MAL_RXEOB (64 + 7) | |
| 254 | #define VECNUM_ETH0 (64 + 16) | |
| 255 | #define VECNUM_ETH1_OFFS 1 | |
| 256 | #endif /* CONFIG_460EX */ | |
| 257 | ||
| 3a82113e SR |
258 | #if defined(CONFIG_460SX) |
| 259 | /* UIC 0 */ | |
| 260 | #define VECNUM_UIC2NCI 10 | |
| 261 | #define VECNUM_UIC2CI 11 | |
| 262 | #define VECNUM_UIC3NCI 16 | |
| 263 | #define VECNUM_UIC3CI 17 | |
| 264 | #define VECNUM_ETH0 19 | |
| 265 | #define VECNUM_ETH1_OFFS 1 | |
| 266 | #define VECNUM_UIC1NCI 30 | |
| 267 | #define VECNUM_UIC1CI 31 | |
| 268 | ||
| 269 | /* UIC 1 */ | |
| 270 | #define VECNUM_MAL_SERR (32 + 1) | |
| 271 | #define VECNUM_MAL_TXDE (32 + 2) | |
| 272 | #define VECNUM_MAL_RXDE (32 + 3) | |
| 273 | #define VECNUM_MAL_TXEOB (32 + 6) | |
| 274 | #define VECNUM_MAL_RXEOB (32 + 7) | |
| 275 | #endif /* CONFIG_460EX */ | |
| 276 | ||
| d1631fe1 SR |
277 | #if !defined(VECNUM_ETH1_OFFS) |
| 278 | #define VECNUM_ETH1_OFFS 1 | |
| 279 | #endif | |
| dbbd1257 | 280 | |
| d1631fe1 SR |
281 | /* |
| 282 | * Mask definitions (used for example in 4xx_enet.c) | |
| 283 | */ | |
| 284 | #define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) | |
| 5de85140 | 285 | /* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ |
| d1631fe1 | 286 | #define UIC_NR(vec) ((vec) >> 5) |
| c609719b | 287 | |
| 4fb25a3d | 288 | #endif /* _PPC4xx_UIC_H_ */ |