[people/ms/u-boot.git] / arch / powerpc / lib / bat_rw.c

/*
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <linux/compiler.h>

#ifdef CONFIG_ADDR_MAP
#include <addr_map.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
	__maybe_unused int batn = -1;

	sync();

	switch (bat) {
	case DBAT0:
		mtspr (DBAT0L, lower);
		mtspr (DBAT0U, upper);
		batn = 0;
		break;
	case IBAT0:
		mtspr (IBAT0L, lower);
		mtspr (IBAT0U, upper);
		break;
	case DBAT1:
		mtspr (DBAT1L, lower);
		mtspr (DBAT1U, upper);
		batn = 1;
		break;
	case IBAT1:
		mtspr (IBAT1L, lower);
		mtspr (IBAT1U, upper);
		break;
	case DBAT2:
		mtspr (DBAT2L, lower);
		mtspr (DBAT2U, upper);
		batn = 2;
		break;
	case IBAT2:
		mtspr (IBAT2L, lower);
		mtspr (IBAT2U, upper);
		break;
	case DBAT3:
		mtspr (DBAT3L, lower);
		mtspr (DBAT3U, upper);
		batn = 3;
		break;
	case IBAT3:
		mtspr (IBAT3L, lower);
		mtspr (IBAT3U, upper);
		break;
#ifdef CONFIG_HIGH_BATS
	case DBAT4:
		mtspr (DBAT4L, lower);
		mtspr (DBAT4U, upper);
		batn = 4;
		break;
	case IBAT4:
		mtspr (IBAT4L, lower);
		mtspr (IBAT4U, upper);
		break;
	case DBAT5:
		mtspr (DBAT5L, lower);
		mtspr (DBAT5U, upper);
		batn = 5;
		break;
	case IBAT5:
		mtspr (IBAT5L, lower);
		mtspr (IBAT5U, upper);
		break;
	case DBAT6:
		mtspr (DBAT6L, lower);
		mtspr (DBAT6U, upper);
		batn = 6;
		break;
	case IBAT6:
		mtspr (IBAT6L, lower);
		mtspr (IBAT6U, upper);
		break;
	case DBAT7:
		mtspr (DBAT7L, lower);
		mtspr (DBAT7U, upper);
		batn = 7;
		break;
	case IBAT7:
		mtspr (IBAT7L, lower);
		mtspr (IBAT7U, upper);
		break;
#endif
	default:
		return (-1);
	}

#ifdef CONFIG_ADDR_MAP
	if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) {
		phys_size_t size;
		if (!BATU_VALID(upper))
			size = 0;
		else
			size = BATU_SIZE(upper);
		addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
				  size, batn);
	}
#endif

	sync();
	isync();

	return (0);
}

int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower)
{
	unsigned long register u;
	unsigned long register l;

	switch (bat) {
	case DBAT0:
		l = mfspr (DBAT0L);
		u = mfspr (DBAT0U);
		break;
	case IBAT0:
		l = mfspr (IBAT0L);
		u = mfspr (IBAT0U);
		break;
	case DBAT1:
		l = mfspr (DBAT1L);
		u = mfspr (DBAT1U);
		break;
	case IBAT1:
		l = mfspr (IBAT1L);
		u = mfspr (IBAT1U);
		break;
	case DBAT2:
		l = mfspr (DBAT2L);
		u = mfspr (DBAT2U);
		break;
	case IBAT2:
		l = mfspr (IBAT2L);
		u = mfspr (IBAT2U);
		break;
	case DBAT3:
		l = mfspr (DBAT3L);
		u = mfspr (DBAT3U);
		break;
	case IBAT3:
		l = mfspr (IBAT3L);
		u = mfspr (IBAT3U);
		break;
#ifdef CONFIG_HIGH_BATS
	case DBAT4:
		l = mfspr (DBAT4L);
		u = mfspr (DBAT4U);
		break;
	case IBAT4:
		l = mfspr (IBAT4L);
		u = mfspr (IBAT4U);
		break;
	case DBAT5:
		l = mfspr (DBAT5L);
		u = mfspr (DBAT5U);
		break;
	case IBAT5:
		l = mfspr (IBAT5L);
		u = mfspr (IBAT5U);
		break;
	case DBAT6:
		l = mfspr (DBAT6L);
		u = mfspr (DBAT6U);
		break;
	case IBAT6:
		l = mfspr (IBAT6L);
		u = mfspr (IBAT6U);
		break;
	case DBAT7:
		l = mfspr (DBAT7L);
		u = mfspr (DBAT7U);
		break;
	case IBAT7:
		l = mfspr (IBAT7L);
		u = mfspr (IBAT7U);
		break;
#endif
	default:
		return (-1);
	}

	*upper = u;
	*lower = l;

	return (0);
}

void print_bats(void)
{
	printf("BAT registers:\n");

	printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L));
	printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U));
	printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L));
	printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U));
	printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L));
	printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U));
	printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L));
	printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U));
	printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L));
	printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U));
	printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L));
	printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U));
	printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L));
	printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U));
	printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L));
	printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U));

#ifdef CONFIG_HIGH_BATS
	printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L));
	printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U));
	printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L));
	printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U));
	printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L));
	printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U));
	printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L));
	printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U));
	printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L));
	printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U));
	printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L));
	printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U));
	printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L));
	printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U));
	printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L));
	printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U));
#endif
}
Commit	Line	Data
affae2bf WD	1	/*
	2	* (C) Copyright 2002
	3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
affae2bf WD	6	*/
	7
	8	#include <common.h>
	9	#include <asm/processor.h>
	10	#include <asm/mmu.h>
9de67149	11	#include <asm/io.h>
8a33201d	12	#include <linux/compiler.h>
affae2bf	13
c9315e6b BB	14	#ifdef CONFIG_ADDR_MAP
	15	#include <addr_map.h>
	16	#endif
	17
	18	DECLARE_GLOBAL_DATA_PTR;
	19
affae2bf WD	20	int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
affae2bf WD	21	{
8a33201d	22	__maybe_unused int batn = -1;
c9315e6b	23
9de67149 BB	24	sync();
9de67149 BB	25
affae2bf	26	switch (bat) {
c148f24c BB	27	case DBAT0:
	28	mtspr (DBAT0L, lower);
	29	mtspr (DBAT0U, upper);
c9315e6b	30	batn = 0;
c148f24c	31	break;
affae2bf WD	32	case IBAT0:
	33	mtspr (IBAT0L, lower);
	34	mtspr (IBAT0U, upper);
	35	break;
c148f24c BB	36	case DBAT1:
	37	mtspr (DBAT1L, lower);
	38	mtspr (DBAT1U, upper);
c9315e6b	39	batn = 1;
c148f24c	40	break;
affae2bf WD	41	case IBAT1:
	42	mtspr (IBAT1L, lower);
	43	mtspr (IBAT1U, upper);
	44	break;
c148f24c BB	45	case DBAT2:
	46	mtspr (DBAT2L, lower);
	47	mtspr (DBAT2U, upper);
c9315e6b	48	batn = 2;
c148f24c	49	break;
affae2bf WD	50	case IBAT2:
	51	mtspr (IBAT2L, lower);
	52	mtspr (IBAT2U, upper);
	53	break;
c148f24c BB	54	case DBAT3:
	55	mtspr (DBAT3L, lower);
	56	mtspr (DBAT3U, upper);
c9315e6b	57	batn = 3;
c148f24c	58	break;
affae2bf WD	59	case IBAT3:
	60	mtspr (IBAT3L, lower);
	61	mtspr (IBAT3U, upper);
	62	break;
c148f24c BB	63	#ifdef CONFIG_HIGH_BATS
	64	case DBAT4:
	65	mtspr (DBAT4L, lower);
	66	mtspr (DBAT4U, upper);
c9315e6b	67	batn = 4;
affae2bf	68	break;
c148f24c BB	69	case IBAT4:
	70	mtspr (IBAT4L, lower);
	71	mtspr (IBAT4U, upper);
affae2bf	72	break;
c148f24c BB	73	case DBAT5:
	74	mtspr (DBAT5L, lower);
	75	mtspr (DBAT5U, upper);
c9315e6b	76	batn = 5;
affae2bf	77	break;
c148f24c BB	78	case IBAT5:
	79	mtspr (IBAT5L, lower);
	80	mtspr (IBAT5U, upper);
affae2bf	81	break;
c148f24c BB	82	case DBAT6:
	83	mtspr (DBAT6L, lower);
	84	mtspr (DBAT6U, upper);
c9315e6b	85	batn = 6;
c148f24c BB	86	break;
	87	case IBAT6:
	88	mtspr (IBAT6L, lower);
	89	mtspr (IBAT6U, upper);
	90	break;
	91	case DBAT7:
	92	mtspr (DBAT7L, lower);
	93	mtspr (DBAT7U, upper);
c9315e6b	94	batn = 7;
c148f24c BB	95	break;
	96	case IBAT7:
	97	mtspr (IBAT7L, lower);
	98	mtspr (IBAT7U, upper);
	99	break;
	100	#endif
affae2bf WD	101	default:
	102	return (-1);
	103	}
	104
c9315e6b BB	105	#ifdef CONFIG_ADDR_MAP
	106	if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) {
	107	phys_size_t size;
	108	if (!BATU_VALID(upper))
	109	size = 0;
	110	else
	111	size = BATU_SIZE(upper);
	112	addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
	113	size, batn);
	114	}
	115	#endif
	116
9de67149 BB	117	sync();
	118	isync();
	119
affae2bf WD	120	return (0);
	121	}
	122
	123	int read_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
	124	{
	125	unsigned long register u;
	126	unsigned long register l;
	127
	128	switch (bat) {
c148f24c BB	129	case DBAT0:
	130	l = mfspr (DBAT0L);
	131	u = mfspr (DBAT0U);
	132	break;
affae2bf WD	133	case IBAT0:
	134	l = mfspr (IBAT0L);
	135	u = mfspr (IBAT0U);
	136	break;
c148f24c BB	137	case DBAT1:
	138	l = mfspr (DBAT1L);
	139	u = mfspr (DBAT1U);
	140	break;
affae2bf WD	141	case IBAT1:
	142	l = mfspr (IBAT1L);
	143	u = mfspr (IBAT1U);
	144	break;
c148f24c BB	145	case DBAT2:
	146	l = mfspr (DBAT2L);
	147	u = mfspr (DBAT2U);
	148	break;
affae2bf WD	149	case IBAT2:
	150	l = mfspr (IBAT2L);
	151	u = mfspr (IBAT2U);
	152	break;
c148f24c BB	153	case DBAT3:
	154	l = mfspr (DBAT3L);
	155	u = mfspr (DBAT3U);
	156	break;
affae2bf WD	157	case IBAT3:
	158	l = mfspr (IBAT3L);
	159	u = mfspr (IBAT3U);
	160	break;
c148f24c BB	161	#ifdef CONFIG_HIGH_BATS
	162	case DBAT4:
	163	l = mfspr (DBAT4L);
	164	u = mfspr (DBAT4U);
affae2bf	165	break;
c148f24c BB	166	case IBAT4:
	167	l = mfspr (IBAT4L);
	168	u = mfspr (IBAT4U);
affae2bf	169	break;
c148f24c BB	170	case DBAT5:
	171	l = mfspr (DBAT5L);
	172	u = mfspr (DBAT5U);
affae2bf	173	break;
c148f24c BB	174	case IBAT5:
	175	l = mfspr (IBAT5L);
	176	u = mfspr (IBAT5U);
affae2bf	177	break;
c148f24c BB	178	case DBAT6:
	179	l = mfspr (DBAT6L);
	180	u = mfspr (DBAT6U);
	181	break;
	182	case IBAT6:
	183	l = mfspr (IBAT6L);
	184	u = mfspr (IBAT6U);
	185	break;
	186	case DBAT7:
	187	l = mfspr (DBAT7L);
	188	u = mfspr (DBAT7U);
	189	break;
	190	case IBAT7:
	191	l = mfspr (IBAT7L);
	192	u = mfspr (IBAT7U);
	193	break;
	194	#endif
affae2bf WD	195	default:
	196	return (-1);
	197	}
	198
	199	*upper = u;
	200	*lower = l;
	201
	202	return (0);
	203	}
d5b9b8cd BB	204
	205	void print_bats(void)
	206	{
	207	printf("BAT registers:\n");
	208
	209	printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L));
	210	printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U));
	211	printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L));
	212	printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U));
	213	printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L));
	214	printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U));
	215	printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L));
	216	printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U));
	217	printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L));
	218	printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U));
	219	printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L));
	220	printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U));
	221	printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L));
	222	printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U));
	223	printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L));
	224	printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U));
	225
	226	#ifdef CONFIG_HIGH_BATS
	227	printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L));
	228	printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U));
	229	printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L));
	230	printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U));
	231	printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L));
	232	printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U));
	233	printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L));
	234	printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U));
	235	printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L));
	236	printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U));
	237	printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L));
	238	printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U));
	239	printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L));
	240	printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U));
	241	printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L));
	242	printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U));
	243	#endif
	244	}