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Commit | Line | Data |
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fe8c2806 | 1 | /* |
9b998b0c | 2 | * (C) Copyright 2000-2011 |
fe8c2806 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
fe8c2806 WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <watchdog.h> | |
10 | #include <command.h> | |
11 | #include <malloc.h> | |
52cb4d4f | 12 | #include <stdio_dev.h> |
fe8c2806 WD |
13 | #ifdef CONFIG_8xx |
14 | #include <mpc8xx.h> | |
15 | #endif | |
0db5bca8 WD |
16 | #ifdef CONFIG_5xx |
17 | #include <mpc5xx.h> | |
18 | #endif | |
cbd8a35c | 19 | #ifdef CONFIG_MPC5xxx |
945af8d7 WD |
20 | #include <mpc5xxx.h> |
21 | #endif | |
7def6b34 | 22 | #if defined(CONFIG_CMD_IDE) |
fe8c2806 WD |
23 | #include <ide.h> |
24 | #endif | |
7def6b34 | 25 | #if defined(CONFIG_CMD_SCSI) |
fe8c2806 WD |
26 | #include <scsi.h> |
27 | #endif | |
7def6b34 | 28 | #if defined(CONFIG_CMD_KGDB) |
fe8c2806 WD |
29 | #include <kgdb.h> |
30 | #endif | |
31 | #ifdef CONFIG_STATUS_LED | |
32 | #include <status_led.h> | |
33 | #endif | |
34 | #include <net.h> | |
272cc70b AF |
35 | #ifdef CONFIG_GENERIC_MMC |
36 | #include <mmc.h> | |
37 | #endif | |
281e00a3 | 38 | #include <serial.h> |
6d0f6bcf | 39 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
9c4c5ae3 | 40 | #if !defined(CONFIG_CPM2) |
fe8c2806 WD |
41 | #include <commproc.h> |
42 | #endif | |
7aa78614 | 43 | #endif |
fe8c2806 WD |
44 | #include <version.h> |
45 | #if defined(CONFIG_BAB7xx) | |
46 | #include <w83c553f.h> | |
47 | #endif | |
48 | #include <dtt.h> | |
49 | #if defined(CONFIG_POST) | |
50 | #include <post.h> | |
51 | #endif | |
56f94be3 WD |
52 | #if defined(CONFIG_LOGBUFFER) |
53 | #include <logbuff.h> | |
54 | #endif | |
9c67352f | 55 | #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) |
42d1f039 WD |
56 | #include <asm/cache.h> |
57 | #endif | |
1c43771b WD |
58 | #ifdef CONFIG_PS2KBD |
59 | #include <keyboard.h> | |
60 | #endif | |
fe8c2806 | 61 | |
ecf5b98c KG |
62 | #ifdef CONFIG_ADDR_MAP |
63 | #include <asm/mmu.h> | |
64 | #endif | |
65 | ||
fc39c2fd KG |
66 | #ifdef CONFIG_MP |
67 | #include <asm/mp.h> | |
68 | #endif | |
69 | ||
310cecb8 LCM |
70 | #ifdef CONFIG_BITBANGMII |
71 | #include <miiphy.h> | |
72 | #endif | |
73 | ||
6d0f6bcf | 74 | #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE |
9b998b0c | 75 | extern int update_flash_size(int flash_size); |
fa230445 HS |
76 | #endif |
77 | ||
9045f33c | 78 | #if defined(CONFIG_SC3) |
ca43ba18 HS |
79 | extern void sc3_read_eeprom(void); |
80 | #endif | |
81 | ||
7def6b34 | 82 | #if defined(CONFIG_CMD_DOC) |
9b998b0c | 83 | void doc_init(void); |
fe8c2806 WD |
84 | #endif |
85 | #if defined(CONFIG_HARD_I2C) || \ | |
86 | defined(CONFIG_SOFT_I2C) | |
87 | #include <i2c.h> | |
88 | #endif | |
04a9e118 | 89 | #include <spi.h> |
d6ac2ed8 | 90 | #include <nand.h> |
fe8c2806 WD |
91 | |
92 | static char *failed = "*** failed ***\n"; | |
93 | ||
544d97e9 | 94 | #if defined(CONFIG_OXC) || defined(CONFIG_RMU) |
fe8c2806 | 95 | extern flash_info_t flash_info[]; |
17d704eb | 96 | #endif |
fe8c2806 | 97 | |
ca43ba18 HS |
98 | #if defined(CONFIG_START_IDE) |
99 | extern int board_start_ide(void); | |
100 | #endif | |
fe8c2806 | 101 | #include <environment.h> |
d87080b7 | 102 | |
bce84c4d | 103 | DECLARE_GLOBAL_DATA_PTR; |
fe8c2806 | 104 | |
6d0f6bcf JCPV |
105 | #if !defined(CONFIG_SYS_MEM_TOP_HIDE) |
106 | #define CONFIG_SYS_MEM_TOP_HIDE 0 | |
6fb4b640 SR |
107 | #endif |
108 | ||
3b57fe0a | 109 | extern ulong __init_end; |
3929fb0a | 110 | extern ulong __bss_end; |
3b57fe0a WD |
111 | ulong monitor_flash_len; |
112 | ||
7def6b34 | 113 | #if defined(CONFIG_CMD_BEDBUG) |
8bde7f77 WD |
114 | #include <bedbug/type.h> |
115 | #endif | |
116 | ||
9b998b0c WD |
117 | /* |
118 | * Utilities | |
fe8c2806 WD |
119 | */ |
120 | ||
fe8c2806 WD |
121 | /* |
122 | * All attempts to come up with a "common" initialization sequence | |
123 | * that works for all boards and architectures failed: some of the | |
124 | * requirements are just _too_ different. To get rid of the resulting | |
125 | * mess of board dependend #ifdef'ed code we now make the whole | |
126 | * initialization sequence configurable to the user. | |
127 | * | |
128 | * The requirements for any new initalization function is simple: it | |
129 | * receives a pointer to the "global data" structure as it's only | |
130 | * argument, and returns an integer return code, where 0 means | |
131 | * "continue" and != 0 means "fatal error, hang the system". | |
132 | */ | |
9b998b0c | 133 | typedef int (init_fnc_t)(void); |
fe8c2806 | 134 | |
9b998b0c WD |
135 | /* |
136 | * Init Utilities | |
137 | * | |
fe8c2806 WD |
138 | * Some of this code should be moved into the core functions, |
139 | * but let's get it working (again) first... | |
140 | */ | |
141 | ||
9b998b0c | 142 | static int init_baudrate(void) |
fe8c2806 | 143 | { |
1272592e SG |
144 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); |
145 | return 0; | |
fe8c2806 WD |
146 | } |
147 | ||
148 | /***********************************************************************/ | |
149 | ||
20051f2a | 150 | static void __board_add_ram_info(int use_default) |
79f240f7 KP |
151 | { |
152 | /* please define platform specific board_add_ram_info() */ | |
153 | } | |
9b998b0c WD |
154 | |
155 | void board_add_ram_info(int) | |
156 | __attribute__ ((weak, alias("__board_add_ram_info"))); | |
79f240f7 | 157 | |
20051f2a | 158 | static int __board_flash_wp_on(void) |
c62491d2 JS |
159 | { |
160 | /* | |
161 | * Most flashes can't be detected when write protection is enabled, | |
162 | * so provide a way to let U-Boot gracefully ignore write protected | |
163 | * devices. | |
164 | */ | |
165 | return 0; | |
166 | } | |
9b998b0c WD |
167 | |
168 | int board_flash_wp_on(void) | |
169 | __attribute__ ((weak, alias("__board_flash_wp_on"))); | |
d96f41e0 | 170 | |
20051f2a | 171 | static void __cpu_secondary_init_r(void) |
f9a33f1c KG |
172 | { |
173 | } | |
9b998b0c | 174 | |
f9a33f1c | 175 | void cpu_secondary_init_r(void) |
9b998b0c | 176 | __attribute__ ((weak, alias("__cpu_secondary_init_r"))); |
f9a33f1c | 177 | |
9b998b0c | 178 | static int init_func_ram(void) |
fe8c2806 | 179 | { |
fe8c2806 WD |
180 | #ifdef CONFIG_BOARD_TYPES |
181 | int board_type = gd->board_type; | |
182 | #else | |
183 | int board_type = 0; /* use dummy arg */ | |
184 | #endif | |
9b998b0c | 185 | puts("DRAM: "); |
fe8c2806 | 186 | |
9b998b0c WD |
187 | gd->ram_size = initdram(board_type); |
188 | ||
189 | if (gd->ram_size > 0) { | |
190 | print_size(gd->ram_size, ""); | |
d96f41e0 | 191 | board_add_ram_info(0); |
d96f41e0 | 192 | putc('\n'); |
9b998b0c | 193 | return 0; |
fe8c2806 | 194 | } |
9b998b0c WD |
195 | puts(failed); |
196 | return 1; | |
fe8c2806 WD |
197 | } |
198 | ||
199 | /***********************************************************************/ | |
200 | ||
201 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) | |
9b998b0c | 202 | static int init_func_i2c(void) |
fe8c2806 | 203 | { |
9b998b0c WD |
204 | puts("I2C: "); |
205 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
206 | puts("ready\n"); | |
207 | return 0; | |
fe8c2806 WD |
208 | } |
209 | #endif | |
210 | ||
04a9e118 | 211 | #if defined(CONFIG_HARD_SPI) |
9b998b0c | 212 | static int init_func_spi(void) |
04a9e118 | 213 | { |
9b998b0c WD |
214 | puts("SPI: "); |
215 | spi_init(); | |
216 | puts("ready\n"); | |
217 | return 0; | |
04a9e118 BW |
218 | } |
219 | #endif | |
220 | ||
fe8c2806 WD |
221 | /***********************************************************************/ |
222 | ||
223 | #if defined(CONFIG_WATCHDOG) | |
a6741bce | 224 | int init_func_watchdog_init(void) |
fe8c2806 | 225 | { |
9b998b0c WD |
226 | puts(" Watchdog enabled\n"); |
227 | WATCHDOG_RESET(); | |
228 | return 0; | |
fe8c2806 | 229 | } |
fe8c2806 | 230 | |
a6741bce | 231 | int init_func_watchdog_reset(void) |
fe8c2806 | 232 | { |
9b998b0c WD |
233 | WATCHDOG_RESET(); |
234 | return 0; | |
fe8c2806 | 235 | } |
fe8c2806 WD |
236 | #endif /* CONFIG_WATCHDOG */ |
237 | ||
9b998b0c WD |
238 | /* |
239 | * Initialization sequence | |
fe8c2806 WD |
240 | */ |
241 | ||
20051f2a | 242 | static init_fnc_t *init_sequence[] = { |
0e870980 PA |
243 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
244 | probecpu, | |
245 | #endif | |
91525c67 AV |
246 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
247 | board_early_init_f, | |
248 | #endif | |
66ca92a5 | 249 | #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) |
fe8c2806 | 250 | get_clocks, /* get CPU and bus clocks (etc.) */ |
090eb735 MK |
251 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ |
252 | && !defined(CONFIG_TQM885D) | |
e9132ea9 WD |
253 | adjust_sdram_tbs_8xx, |
254 | #endif | |
fe8c2806 | 255 | init_timebase, |
c178d3da | 256 | #endif |
6d0f6bcf | 257 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
9c4c5ae3 | 258 | #if !defined(CONFIG_CPM2) |
fe8c2806 WD |
259 | dpram_init, |
260 | #endif | |
7aa78614 | 261 | #endif |
fe8c2806 WD |
262 | #if defined(CONFIG_BOARD_POSTCLK_INIT) |
263 | board_postclk_init, | |
264 | #endif | |
265 | env_init, | |
66ca92a5 | 266 | #if defined(CONFIG_8xx_CPUCLK_DEFAULT) |
9b998b0c WD |
267 | /* get CPU and bus clocks according to the environment variable */ |
268 | get_clocks_866, | |
269 | /* adjust sdram refresh rate according to the new clock */ | |
270 | sdram_adjust_866, | |
c178d3da WD |
271 | init_timebase, |
272 | #endif | |
fe8c2806 WD |
273 | init_baudrate, |
274 | serial_init, | |
275 | console_init_f, | |
276 | display_options, | |
277 | #if defined(CONFIG_8260) | |
278 | prt_8260_rsr, | |
279 | prt_8260_clks, | |
280 | #endif /* CONFIG_8260 */ | |
0f898604 | 281 | #if defined(CONFIG_MPC83xx) |
9be39a67 DL |
282 | prt_83xx_rsr, |
283 | #endif | |
fe8c2806 | 284 | checkcpu, |
cbd8a35c | 285 | #if defined(CONFIG_MPC5xxx) |
945af8d7 | 286 | prt_mpc5xxx_clks, |
cbd8a35c | 287 | #endif /* CONFIG_MPC5xxx */ |
fe8c2806 WD |
288 | checkboard, |
289 | INIT_FUNC_WATCHDOG_INIT | |
c837dcb1 | 290 | #if defined(CONFIG_MISC_INIT_F) |
fe8c2806 WD |
291 | misc_init_f, |
292 | #endif | |
293 | INIT_FUNC_WATCHDOG_RESET | |
294 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) | |
295 | init_func_i2c, | |
296 | #endif | |
04a9e118 BW |
297 | #if defined(CONFIG_HARD_SPI) |
298 | init_func_spi, | |
299 | #endif | |
4532cb69 WD |
300 | #ifdef CONFIG_POST |
301 | post_init_f, | |
fe8c2806 | 302 | #endif |
6f6430d7 SG |
303 | INIT_FUNC_WATCHDOG_RESET |
304 | init_func_ram, | |
6d0f6bcf | 305 | #if defined(CONFIG_SYS_DRAM_TEST) |
fe8c2806 | 306 | testdram, |
6d0f6bcf | 307 | #endif /* CONFIG_SYS_DRAM_TEST */ |
fe8c2806 | 308 | INIT_FUNC_WATCHDOG_RESET |
9b998b0c | 309 | NULL, /* Terminate this list */ |
fe8c2806 WD |
310 | }; |
311 | ||
81d93e5c KG |
312 | ulong get_effective_memsize(void) |
313 | { | |
314 | #ifndef CONFIG_VERY_BIG_RAM | |
315 | return gd->ram_size; | |
316 | #else | |
317 | /* limit stack to what we can reasonable map */ | |
318 | return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? | |
9b998b0c | 319 | CONFIG_MAX_MEM_MAPPED : gd->ram_size); |
81d93e5c KG |
320 | #endif |
321 | } | |
322 | ||
20051f2a | 323 | static int __fixup_cpu(void) |
123bd96d YS |
324 | { |
325 | return 0; | |
326 | } | |
327 | ||
328 | int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu"))); | |
329 | ||
9b998b0c | 330 | /* |
fe8c2806 WD |
331 | * This is the first part of the initialization sequence that is |
332 | * implemented in C, but still running from ROM. | |
333 | * | |
334 | * The main purpose is to provide a (serial) console interface as | |
335 | * soon as possible (so we can see any error messages), and to | |
336 | * initialize the RAM so that we can relocate the monitor code to | |
337 | * RAM. | |
338 | * | |
339 | * Be aware of the restrictions: global data is read-only, BSS is not | |
340 | * initialized, and stack space is limited to a few kB. | |
fe8c2806 WD |
341 | */ |
342 | ||
95d449ad MB |
343 | #ifdef CONFIG_LOGBUFFER |
344 | unsigned long logbuffer_base(void) | |
345 | { | |
6d0f6bcf | 346 | return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN; |
95d449ad MB |
347 | } |
348 | #endif | |
349 | ||
9b998b0c | 350 | void board_init_f(ulong bootflag) |
fe8c2806 | 351 | { |
fe8c2806 WD |
352 | bd_t *bd; |
353 | ulong len, addr, addr_sp; | |
7bc5ee07 | 354 | ulong *s; |
fe8c2806 WD |
355 | gd_t *id; |
356 | init_fnc_t **init_fnc_ptr; | |
9b998b0c | 357 | |
fe8c2806 | 358 | #ifdef CONFIG_PRAM |
fe8c2806 | 359 | ulong reg; |
fe8c2806 WD |
360 | #endif |
361 | ||
362 | /* Pointer is writable since we allocated a register for it */ | |
6d0f6bcf | 363 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
93f6a677 | 364 | /* compiler optimization barrier needed for GCC >= 3.4 */ |
9b998b0c | 365 | __asm__ __volatile__("":::"memory"); |
fe8c2806 | 366 | |
82826d54 DZ |
367 | #if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ |
368 | !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ | |
369 | !defined(CONFIG_MPC86xx) | |
fe8c2806 | 370 | /* Clear initial global data */ |
9b998b0c | 371 | memset((void *) gd, 0, sizeof(gd_t)); |
fe8c2806 WD |
372 | #endif |
373 | ||
9b998b0c WD |
374 | for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) |
375 | if ((*init_fnc_ptr) () != 0) | |
376 | hang(); | |
fe8c2806 | 377 | |
9d256b67 BK |
378 | #ifdef CONFIG_POST |
379 | post_bootmode_init(); | |
20051f2a | 380 | post_run(NULL, POST_ROM | post_bootmode_get(NULL)); |
9d256b67 BK |
381 | #endif |
382 | ||
383 | WATCHDOG_RESET(); | |
384 | ||
fe8c2806 WD |
385 | /* |
386 | * Now that we have DRAM mapped and working, we can | |
387 | * relocate the code and continue running from DRAM. | |
388 | * | |
389 | * Reserve memory at end of RAM for (top down in that order): | |
14f73ca6 | 390 | * - area that won't get touched by U-Boot and Linux (optional) |
8bde7f77 | 391 | * - kernel log buffer |
fe8c2806 WD |
392 | * - protected RAM |
393 | * - LCD framebuffer | |
394 | * - monitor code | |
395 | * - board info struct | |
396 | */ | |
3929fb0a | 397 | len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; |
fe8c2806 | 398 | |
14f73ca6 SR |
399 | /* |
400 | * Subtract specified amount of memory to hide so that it won't | |
401 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
402 | * the Linux kernel should now get passed the now "corrected" | |
403 | * memory size and won't touch it either. This should work | |
404 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
405 | * arch/powerpc with bootwrapper support, that recalculate the | |
406 | * memory size from the SDRAM controller setup will have to | |
407 | * get fixed. | |
408 | */ | |
6d0f6bcf | 409 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; |
14f73ca6 | 410 | |
6d0f6bcf | 411 | addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize(); |
fe8c2806 | 412 | |
fc39c2fd KG |
413 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
414 | /* | |
415 | * We need to make sure the location we intend to put secondary core | |
416 | * boot code is reserved and not used by any part of u-boot | |
c0a14aed | 417 | */ |
eb539412 YS |
418 | if (addr > determine_mp_bootpg(NULL)) { |
419 | addr = determine_mp_bootpg(NULL); | |
9b998b0c | 420 | debug("Reserving MP boot page to %08lx\n", addr); |
fc39c2fd KG |
421 | } |
422 | #endif | |
423 | ||
228f29ac | 424 | #ifdef CONFIG_LOGBUFFER |
3d610186 | 425 | #ifndef CONFIG_ALT_LB_ADDR |
228f29ac WD |
426 | /* reserve kernel log buffer */ |
427 | addr -= (LOGBUFF_RESERVE); | |
9b998b0c WD |
428 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
429 | addr); | |
228f29ac | 430 | #endif |
3d610186 | 431 | #endif |
228f29ac | 432 | |
fe8c2806 WD |
433 | #ifdef CONFIG_PRAM |
434 | /* | |
435 | * reserve protected RAM | |
436 | */ | |
1272592e | 437 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); |
9b998b0c | 438 | addr -= (reg << 10); /* size is in kB */ |
1272592e | 439 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr); |
fe8c2806 WD |
440 | #endif /* CONFIG_PRAM */ |
441 | ||
442 | /* round down to next 4 kB limit */ | |
443 | addr &= ~(4096 - 1); | |
9b998b0c | 444 | debug("Top of RAM usable for U-Boot at: %08lx\n", addr); |
fe8c2806 WD |
445 | |
446 | #ifdef CONFIG_LCD | |
d32a1a4c MK |
447 | #ifdef CONFIG_FB_ADDR |
448 | gd->fb_base = CONFIG_FB_ADDR; | |
449 | #else | |
fe8c2806 | 450 | /* reserve memory for LCD display (always full pages) */ |
9b998b0c | 451 | addr = lcd_setmem(addr); |
fe8c2806 | 452 | gd->fb_base = addr; |
d32a1a4c | 453 | #endif /* CONFIG_FB_ADDR */ |
fe8c2806 WD |
454 | #endif /* CONFIG_LCD */ |
455 | ||
456 | #if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) | |
457 | /* reserve memory for video display (always full pages) */ | |
9b998b0c | 458 | addr = video_setmem(addr); |
fe8c2806 WD |
459 | gd->fb_base = addr; |
460 | #endif /* CONFIG_VIDEO */ | |
461 | ||
462 | /* | |
463 | * reserve memory for U-Boot code, data & bss | |
682011ff | 464 | * round down to next 4 kB limit |
fe8c2806 WD |
465 | */ |
466 | addr -= len; | |
682011ff | 467 | addr &= ~(4096 - 1); |
7d314992 WD |
468 | #ifdef CONFIG_E500 |
469 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
470 | addr &= ~(65536 - 1); | |
471 | #endif | |
fe8c2806 | 472 | |
9b998b0c | 473 | debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); |
fe8c2806 WD |
474 | |
475 | /* | |
476 | * reserve memory for malloc() arena | |
477 | */ | |
478 | addr_sp = addr - TOTAL_MALLOC_LEN; | |
9b998b0c WD |
479 | debug("Reserving %dk for malloc() at: %08lx\n", |
480 | TOTAL_MALLOC_LEN >> 10, addr_sp); | |
fe8c2806 WD |
481 | |
482 | /* | |
483 | * (permanently) allocate a Board Info struct | |
484 | * and a permanent copy of the "global" data | |
485 | */ | |
9b998b0c | 486 | addr_sp -= sizeof(bd_t); |
fe8c2806 | 487 | bd = (bd_t *) addr_sp; |
a1c4864a | 488 | memset(bd, 0, sizeof(bd_t)); |
fe8c2806 | 489 | gd->bd = bd; |
9b998b0c WD |
490 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", |
491 | sizeof(bd_t), addr_sp); | |
492 | addr_sp -= sizeof(gd_t); | |
fe8c2806 | 493 | id = (gd_t *) addr_sp; |
9b998b0c WD |
494 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
495 | sizeof(gd_t), addr_sp); | |
fe8c2806 WD |
496 | |
497 | /* | |
498 | * Finally, we set up a new (bigger) stack. | |
499 | * | |
500 | * Leave some safety gap for SP, force alignment on 16 byte boundary | |
501 | * Clear initial stack frame | |
502 | */ | |
503 | addr_sp -= 16; | |
504 | addr_sp &= ~0xF; | |
9b998b0c | 505 | s = (ulong *) addr_sp; |
7de8a716 JT |
506 | *s = 0; /* Terminate back chain */ |
507 | *++s = 0; /* NULL return address */ | |
9b998b0c | 508 | debug("Stack Pointer at: %08lx\n", addr_sp); |
fe8c2806 WD |
509 | |
510 | /* | |
511 | * Save local variables to board info struct | |
512 | */ | |
513 | ||
9b998b0c WD |
514 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ |
515 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
fe8c2806 | 516 | |
36116650 | 517 | #ifdef CONFIG_SYS_SRAM_BASE |
9b998b0c WD |
518 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ |
519 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
fe8c2806 WD |
520 | #endif |
521 | ||
42d1f039 | 522 | #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ |
debb7354 | 523 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
6d0f6bcf | 524 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ |
fe8c2806 | 525 | #endif |
cbd8a35c | 526 | #if defined(CONFIG_MPC5xxx) |
6d0f6bcf | 527 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
945af8d7 | 528 | #endif |
0f898604 | 529 | #if defined(CONFIG_MPC83xx) |
6d0f6bcf | 530 | bd->bi_immrbar = CONFIG_SYS_IMMR; |
f046ccd1 | 531 | #endif |
fe8c2806 | 532 | |
9b998b0c | 533 | WATCHDOG_RESET(); |
fe8c2806 WD |
534 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ |
535 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
9c4c5ae3 | 536 | #if defined(CONFIG_CPM2) |
748cd059 | 537 | bd->bi_cpmfreq = gd->arch.cpm_clk; |
1206c184 | 538 | bd->bi_brgfreq = gd->arch.brg_clk; |
748cd059 SG |
539 | bd->bi_sccfreq = gd->arch.scc_clk; |
540 | bd->bi_vco = gd->arch.vco_out; | |
9c4c5ae3 | 541 | #endif /* CONFIG_CPM2 */ |
281ff9a4 | 542 | #if defined(CONFIG_MPC512X) |
fefb098b | 543 | bd->bi_ipsfreq = gd->arch.ips_clk; |
281ff9a4 | 544 | #endif /* CONFIG_MPC512X */ |
cbd8a35c | 545 | #if defined(CONFIG_MPC5xxx) |
b2877496 | 546 | bd->bi_ipbfreq = gd->arch.ipb_clk; |
945af8d7 | 547 | bd->bi_pcifreq = gd->pci_clk; |
cbd8a35c | 548 | #endif /* CONFIG_MPC5xxx */ |
fe8c2806 WD |
549 | bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ |
550 | ||
6d0f6bcf | 551 | #ifdef CONFIG_SYS_EXTBDINFO |
9b998b0c WD |
552 | strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); |
553 | strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, | |
554 | sizeof(bd->bi_r_version)); | |
fe8c2806 WD |
555 | |
556 | bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ | |
557 | bd->bi_plb_busfreq = gd->bus_clk; | |
343c48bd SR |
558 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ |
559 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
560 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
9b998b0c WD |
561 | bd->bi_pci_busfreq = get_PCI_freq(); |
562 | bd->bi_opbfreq = get_OPB_freq(); | |
9fea65a6 | 563 | #elif defined(CONFIG_XILINX_405) |
9b998b0c | 564 | bd->bi_pci_busfreq = get_PCI_freq(); |
fe8c2806 WD |
565 | #endif |
566 | #endif | |
567 | ||
9b998b0c | 568 | debug("New Stack Pointer is: %08lx\n", addr_sp); |
fe8c2806 | 569 | |
9b998b0c | 570 | WATCHDOG_RESET(); |
fe8c2806 | 571 | |
9b998b0c | 572 | gd->relocaddr = addr; /* Store relocation addr, useful for debug */ |
4b99327a | 573 | |
9b998b0c | 574 | memcpy(id, (void *) gd, sizeof(gd_t)); |
fe8c2806 | 575 | |
9b998b0c | 576 | relocate_code(addr_sp, id, addr); |
fe8c2806 WD |
577 | |
578 | /* NOTREACHED - relocate_code() does not return */ | |
579 | } | |
580 | ||
9b998b0c | 581 | /* |
fe8c2806 WD |
582 | * This is the next part if the initialization sequence: we are now |
583 | * running from RAM and have a "normal" C environment, i. e. global | |
584 | * data can be written, BSS has been cleared, the stack size in not | |
585 | * that critical any more, etc. | |
fe8c2806 | 586 | */ |
9b998b0c | 587 | void board_init_r(gd_t *id, ulong dest_addr) |
fe8c2806 | 588 | { |
fe8c2806 | 589 | bd_t *bd; |
a483a167 | 590 | ulong malloc_start; |
9b998b0c | 591 | |
6d0f6bcf | 592 | #ifndef CONFIG_SYS_NO_FLASH |
fe8c2806 WD |
593 | ulong flash_size; |
594 | #endif | |
595 | ||
596 | gd = id; /* initialize RAM version of global data */ | |
597 | bd = gd->bd; | |
598 | ||
599 | gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ | |
f82b3b63 | 600 | |
d4e8ada0 | 601 | /* The Malloc area is immediately below the monitor copy in DRAM */ |
a483a167 | 602 | malloc_start = dest_addr - TOTAL_MALLOC_LEN; |
13d46ab2 | 603 | |
f9476902 PT |
604 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
605 | /* | |
67ac13b1 SG |
606 | * The gd->arch.cpu pointer is set to an address in flash before |
607 | * relocation. We need to update it to point to the same CPU entry | |
608 | * in RAM. | |
f9476902 | 609 | */ |
67ac13b1 | 610 | gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE; |
123bd96d YS |
611 | |
612 | /* | |
613 | * If we didn't know the cpu mask & # cores, we can save them of | |
614 | * now rather than 'computing' them constantly | |
615 | */ | |
616 | fixup_cpu(); | |
a55bb834 KG |
617 | #endif |
618 | ||
619 | #ifdef CONFIG_SYS_EXTRA_ENV_RELOC | |
620 | /* | |
621 | * Some systems need to relocate the env_addr pointer early because the | |
622 | * location it points to will get invalidated before env_relocate is | |
623 | * called. One example is on systems that might use a L2 or L3 cache | |
624 | * in SRAM mode and initialize that cache from SRAM mode back to being | |
625 | * a cache in cpu_init_r. | |
626 | */ | |
627 | gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE; | |
f9476902 PT |
628 | #endif |
629 | ||
bb105f24 | 630 | serial_initialize(); |
fe8c2806 | 631 | |
9b998b0c | 632 | debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); |
fe8c2806 | 633 | |
9b998b0c | 634 | WATCHDOG_RESET(); |
fe8c2806 | 635 | |
d025aa4b BB |
636 | /* |
637 | * Setup trap handlers | |
638 | */ | |
9b998b0c | 639 | trap_init(dest_addr); |
d025aa4b | 640 | |
c9315e6b | 641 | #ifdef CONFIG_ADDR_MAP |
ecf5b98c KG |
642 | init_addr_map(); |
643 | #endif | |
644 | ||
c837dcb1 | 645 | #if defined(CONFIG_BOARD_EARLY_INIT_R) |
9b998b0c | 646 | board_early_init_r(); |
c837dcb1 WD |
647 | #endif |
648 | ||
3b57fe0a | 649 | monitor_flash_len = (ulong)&__init_end - dest_addr; |
fe8c2806 | 650 | |
9b998b0c | 651 | WATCHDOG_RESET(); |
fe8c2806 | 652 | |
56f94be3 | 653 | #ifdef CONFIG_LOGBUFFER |
9b998b0c | 654 | logbuff_init_ptrs(); |
56f94be3 | 655 | #endif |
fe8c2806 | 656 | #ifdef CONFIG_POST |
9b998b0c | 657 | post_output_backlog(); |
fe8c2806 WD |
658 | #endif |
659 | ||
660 | WATCHDOG_RESET(); | |
661 | ||
1a2e203b | 662 | #if defined(CONFIG_SYS_DELAYED_ICACHE) |
9b998b0c | 663 | icache_enable(); /* it's time to enable the instruction cache */ |
fe8c2806 WD |
664 | #endif |
665 | ||
9c67352f WD |
666 | #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) |
667 | unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ | |
42d1f039 WD |
668 | #endif |
669 | ||
76221a6c | 670 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) |
fe8c2806 | 671 | /* |
76221a6c AS |
672 | * Do early PCI configuration _before_ the flash gets initialised, |
673 | * because PCU ressources are crucial for flash access on some boards. | |
fe8c2806 | 674 | */ |
9b998b0c | 675 | pci_init(); |
3bac3513 | 676 | #endif |
57d6c589 | 677 | #if defined(CONFIG_WINBOND_83C553) |
fe8c2806 WD |
678 | /* |
679 | * Initialise the ISA bridge | |
680 | */ | |
9b998b0c | 681 | initialise_w83c553f(); |
fe8c2806 WD |
682 | #endif |
683 | ||
9b998b0c | 684 | asm("sync ; isync"); |
fe8c2806 | 685 | |
9b998b0c | 686 | mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN); |
c790b04d | 687 | |
6d0f6bcf | 688 | #if !defined(CONFIG_SYS_NO_FLASH) |
9b998b0c | 689 | puts("Flash: "); |
fe8c2806 | 690 | |
c62491d2 JS |
691 | if (board_flash_wp_on()) { |
692 | printf("Uninitialized - Write Protect On\n"); | |
693 | /* Since WP is on, we can't find real size. Set to 0 */ | |
694 | flash_size = 0; | |
9b998b0c WD |
695 | } else if ((flash_size = flash_init()) > 0) { |
696 | #ifdef CONFIG_SYS_FLASH_CHECKSUM | |
9b998b0c | 697 | print_size(flash_size, ""); |
fe8c2806 WD |
698 | /* |
699 | * Compute and print flash CRC if flashchecksum is set to 'y' | |
700 | * | |
701 | * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX | |
702 | */ | |
ec8a252c | 703 | if (getenv_yesno("flashchecksum") == 1) { |
9b998b0c WD |
704 | printf(" CRC: %08X", |
705 | crc32(0, | |
706 | (const unsigned char *) | |
707 | CONFIG_SYS_FLASH_BASE, flash_size) | |
708 | ); | |
fe8c2806 | 709 | } |
9b998b0c WD |
710 | putc('\n'); |
711 | #else /* !CONFIG_SYS_FLASH_CHECKSUM */ | |
712 | print_size(flash_size, "\n"); | |
713 | #endif /* CONFIG_SYS_FLASH_CHECKSUM */ | |
fe8c2806 | 714 | } else { |
9b998b0c WD |
715 | puts(failed); |
716 | hang(); | |
fe8c2806 WD |
717 | } |
718 | ||
9b998b0c WD |
719 | /* update start of FLASH memory */ |
720 | bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; | |
721 | /* size of FLASH memory (final value) */ | |
722 | bd->bi_flashsize = flash_size; | |
fa230445 | 723 | |
6d0f6bcf | 724 | #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) |
fa230445 | 725 | /* Make a update of the Memctrl. */ |
9b998b0c | 726 | update_flash_size(flash_size); |
fa230445 HS |
727 | #endif |
728 | ||
729 | ||
9b998b0c | 730 | #if defined(CONFIG_OXC) || defined(CONFIG_RMU) |
7e780369 | 731 | /* flash mapped at end of memory map */ |
14d0a02a | 732 | bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size; |
9b998b0c WD |
733 | #elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE |
734 | bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */ | |
735 | #endif | |
6d0f6bcf | 736 | #endif /* !CONFIG_SYS_NO_FLASH */ |
fe8c2806 | 737 | |
9b998b0c | 738 | WATCHDOG_RESET(); |
fe8c2806 WD |
739 | |
740 | /* initialize higher level parts of CPU like time base and timers */ | |
9b998b0c | 741 | cpu_init_r(); |
fe8c2806 | 742 | |
9b998b0c | 743 | WATCHDOG_RESET(); |
fe8c2806 | 744 | |
fe8c2806 | 745 | #ifdef CONFIG_SPI |
9b998b0c WD |
746 | #if !defined(CONFIG_ENV_IS_IN_EEPROM) |
747 | spi_init_f(); | |
748 | #endif | |
749 | spi_init_r(); | |
fe8c2806 WD |
750 | #endif |
751 | ||
7def6b34 | 752 | #if defined(CONFIG_CMD_NAND) |
9b998b0c WD |
753 | WATCHDOG_RESET(); |
754 | puts("NAND: "); | |
887e2ec9 SR |
755 | nand_init(); /* go init the NAND */ |
756 | #endif | |
757 | ||
a8060359 TL |
758 | #ifdef CONFIG_GENERIC_MMC |
759 | /* | |
760 | * MMC initialization is called before relocating env. | |
761 | * Thus It is required that operations like pin multiplexer | |
762 | * be put in board_init. | |
763 | */ | |
9b998b0c WD |
764 | WATCHDOG_RESET(); |
765 | puts("MMC: "); | |
766 | mmc_initialize(bd); | |
a8060359 TL |
767 | #endif |
768 | ||
fe8c2806 | 769 | /* relocate environment function pointers etc. */ |
9b998b0c | 770 | env_relocate(); |
fe8c2806 | 771 | |
f9a33f1c KG |
772 | /* |
773 | * after non-volatile devices & environment is setup and cpu code have | |
774 | * another round to deal with any initialization that might require | |
775 | * full access to the environment or loading of some image (firmware) | |
776 | * from a non-volatile device | |
777 | */ | |
778 | cpu_secondary_init_r(); | |
779 | ||
fe8c2806 WD |
780 | /* |
781 | * Fill in missing fields of bd_info. | |
8bde7f77 WD |
782 | * We do this here, where we have "normal" access to the |
783 | * environment; we used to do this still running from ROM, | |
cdb74977 | 784 | * where had to use getenv_f(), which can be pretty slow when |
8bde7f77 | 785 | * the environment is in EEPROM. |
fe8c2806 | 786 | */ |
7abf0c58 | 787 | |
6d0f6bcf | 788 | #if defined(CONFIG_SYS_EXTBDINFO) |
7abf0c58 WD |
789 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) |
790 | #if defined(CONFIG_I2CFAST) | |
791 | /* | |
792 | * set bi_iic_fast for linux taking environment variable | |
793 | * "i2cfast" into account | |
794 | */ | |
795 | { | |
ec8a252c | 796 | if (getenv_yesno("i2cfast") == 1) { |
7abf0c58 WD |
797 | bd->bi_iic_fast[0] = 1; |
798 | bd->bi_iic_fast[1] = 1; | |
7abf0c58 WD |
799 | } |
800 | } | |
9b998b0c WD |
801 | #endif /* CONFIG_I2CFAST */ |
802 | #endif /* CONFIG_405GP, CONFIG_405EP */ | |
803 | #endif /* CONFIG_SYS_EXTBDINFO */ | |
7abf0c58 | 804 | |
9045f33c | 805 | #if defined(CONFIG_SC3) |
ca43ba18 HS |
806 | sc3_read_eeprom(); |
807 | #endif | |
d59feffb | 808 | |
9b998b0c | 809 | #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) |
d59feffb HW |
810 | mac_read_from_eeprom(); |
811 | #endif | |
812 | ||
fe8c2806 WD |
813 | #ifdef CONFIG_HERMES |
814 | if ((gd->board_type >> 16) == 2) | |
815 | bd->bi_ethspeed = gd->board_type & 0xFFFF; | |
816 | else | |
817 | bd->bi_ethspeed = 0xFFFF; | |
818 | #endif | |
819 | ||
02a301cd | 820 | #ifdef CONFIG_CMD_NET |
eb85aa59 MF |
821 | /* kept around for legacy kernels only ... ignore the next section */ |
822 | eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr); | |
e2ffd59b | 823 | #ifdef CONFIG_HAS_ETH1 |
eb85aa59 | 824 | eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr); |
fe8c2806 | 825 | #endif |
e2ffd59b | 826 | #ifdef CONFIG_HAS_ETH2 |
eb85aa59 | 827 | eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr); |
fe8c2806 | 828 | #endif |
e2ffd59b | 829 | #ifdef CONFIG_HAS_ETH3 |
eb85aa59 | 830 | eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr); |
ba56f625 | 831 | #endif |
c68a05fe | 832 | #ifdef CONFIG_HAS_ETH4 |
eb85aa59 | 833 | eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr); |
c68a05fe | 834 | #endif |
c68a05fe | 835 | #ifdef CONFIG_HAS_ETH5 |
eb85aa59 | 836 | eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr); |
c68a05fe | 837 | #endif |
02a301cd | 838 | #endif /* CONFIG_CMD_NET */ |
c68a05fe | 839 | |
9b998b0c | 840 | WATCHDOG_RESET(); |
fe8c2806 | 841 | |
76221a6c | 842 | #if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) |
fe8c2806 WD |
843 | /* |
844 | * Do pci configuration | |
845 | */ | |
9b998b0c | 846 | pci_init(); |
fe8c2806 WD |
847 | #endif |
848 | ||
849 | /** leave this here (after malloc(), environment and PCI are working) **/ | |
52cb4d4f | 850 | /* Initialize stdio devices */ |
9b998b0c | 851 | stdio_init(); |
fe8c2806 | 852 | |
27b207fd | 853 | /* Initialize the jump table for applications */ |
9b998b0c | 854 | jumptable_init(); |
fe8c2806 | 855 | |
500856eb RJ |
856 | #if defined(CONFIG_API) |
857 | /* Initialize API */ | |
9b998b0c | 858 | api_init(); |
500856eb RJ |
859 | #endif |
860 | ||
fe8c2806 | 861 | /* Initialize the console (after the relocation and devices init) */ |
9b998b0c | 862 | console_init_r(); |
fe8c2806 | 863 | |
3a8f28d0 | 864 | #if defined(CONFIG_MISC_INIT_R) |
fe8c2806 | 865 | /* miscellaneous platform dependent initialisations */ |
9b998b0c | 866 | misc_init_r(); |
fe8c2806 WD |
867 | #endif |
868 | ||
869 | #ifdef CONFIG_HERMES | |
870 | if (bd->bi_ethspeed != 0xFFFF) | |
9b998b0c | 871 | hermes_start_lxt980((int) bd->bi_ethspeed); |
fe8c2806 WD |
872 | #endif |
873 | ||
7def6b34 | 874 | #if defined(CONFIG_CMD_KGDB) |
9b998b0c WD |
875 | WATCHDOG_RESET(); |
876 | puts("KGDB: "); | |
877 | kgdb_init(); | |
fe8c2806 WD |
878 | #endif |
879 | ||
9b998b0c | 880 | debug("U-Boot relocated to %08lx\n", dest_addr); |
fe8c2806 WD |
881 | |
882 | /* | |
883 | * Enable Interrupts | |
884 | */ | |
9b998b0c | 885 | interrupt_init(); |
fe8c2806 | 886 | |
566a494f | 887 | #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) |
9b998b0c | 888 | status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); |
fe8c2806 WD |
889 | #endif |
890 | ||
9b998b0c | 891 | udelay(20); |
fe8c2806 | 892 | |
fe8c2806 | 893 | /* Initialize from environment */ |
1272592e | 894 | load_addr = getenv_ulong("loadaddr", 16, load_addr); |
fe8c2806 | 895 | |
9b998b0c | 896 | WATCHDOG_RESET(); |
fe8c2806 | 897 | |
7def6b34 | 898 | #if defined(CONFIG_CMD_SCSI) |
9b998b0c WD |
899 | WATCHDOG_RESET(); |
900 | puts("SCSI: "); | |
901 | scsi_init(); | |
fe8c2806 WD |
902 | #endif |
903 | ||
7def6b34 | 904 | #if defined(CONFIG_CMD_DOC) |
9b998b0c WD |
905 | WATCHDOG_RESET(); |
906 | puts("DOC: "); | |
907 | doc_init(); | |
fe8c2806 WD |
908 | #endif |
909 | ||
310cecb8 LCM |
910 | #ifdef CONFIG_BITBANGMII |
911 | bb_miiphy_init(); | |
912 | #endif | |
7def6b34 | 913 | #if defined(CONFIG_CMD_NET) |
9b998b0c WD |
914 | WATCHDOG_RESET(); |
915 | puts("Net: "); | |
916 | eth_initialize(bd); | |
fe8c2806 WD |
917 | #endif |
918 | ||
004eca0c | 919 | #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) |
9b998b0c WD |
920 | WATCHDOG_RESET(); |
921 | debug("Reset Ethernet PHY\n"); | |
922 | reset_phy(); | |
63ff004c MB |
923 | #endif |
924 | ||
fe8c2806 | 925 | #ifdef CONFIG_POST |
9b998b0c | 926 | post_run(NULL, POST_RAM | post_bootmode_get(0)); |
fe8c2806 WD |
927 | #endif |
928 | ||
7def6b34 JL |
929 | #if defined(CONFIG_CMD_PCMCIA) \ |
930 | && !defined(CONFIG_CMD_IDE) | |
9b998b0c WD |
931 | WATCHDOG_RESET(); |
932 | puts("PCMCIA:"); | |
933 | pcmcia_init(); | |
fe8c2806 WD |
934 | #endif |
935 | ||
7def6b34 | 936 | #if defined(CONFIG_CMD_IDE) |
9b998b0c WD |
937 | WATCHDOG_RESET(); |
938 | #ifdef CONFIG_IDE_8xx_PCCARD | |
939 | puts("PCMCIA:"); | |
940 | #else | |
941 | puts("IDE: "); | |
fe8c2806 | 942 | #endif |
ca43ba18 HS |
943 | #if defined(CONFIG_START_IDE) |
944 | if (board_start_ide()) | |
9b998b0c | 945 | ide_init(); |
ca43ba18 | 946 | #else |
9b998b0c | 947 | ide_init(); |
ca43ba18 | 948 | #endif |
b3aff0cb | 949 | #endif |
fe8c2806 WD |
950 | |
951 | #ifdef CONFIG_LAST_STAGE_INIT | |
9b998b0c | 952 | WATCHDOG_RESET(); |
fe8c2806 WD |
953 | /* |
954 | * Some parts can be only initialized if all others (like | |
955 | * Interrupts) are up and running (i.e. the PC-style ISA | |
956 | * keyboard). | |
957 | */ | |
9b998b0c | 958 | last_stage_init(); |
fe8c2806 WD |
959 | #endif |
960 | ||
7def6b34 | 961 | #if defined(CONFIG_CMD_BEDBUG) |
9b998b0c WD |
962 | WATCHDOG_RESET(); |
963 | bedbug_init(); | |
fe8c2806 WD |
964 | #endif |
965 | ||
228f29ac | 966 | #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) |
fe8c2806 WD |
967 | /* |
968 | * Export available size of memory for Linux, | |
969 | * taking into account the protected RAM at top of memory | |
970 | */ | |
971 | { | |
1272592e | 972 | ulong pram = 0; |
d01b1761 | 973 | char memsz[32]; |
fe8c2806 | 974 | |
1272592e SG |
975 | #ifdef CONFIG_PRAM |
976 | pram = getenv_ulong("pram", 10, CONFIG_PRAM); | |
228f29ac WD |
977 | #endif |
978 | #ifdef CONFIG_LOGBUFFER | |
3d610186 | 979 | #ifndef CONFIG_ALT_LB_ADDR |
228f29ac | 980 | /* Also take the logbuffer into account (pram is in kB) */ |
9b998b0c | 981 | pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; |
3d610186 | 982 | #endif |
228f29ac | 983 | #endif |
d01b1761 SG |
984 | sprintf(memsz, "%ldk", (bd->bi_memsize / 1024) - pram); |
985 | setenv("mem", memsz); | |
fe8c2806 WD |
986 | } |
987 | #endif | |
988 | ||
1c43771b | 989 | #ifdef CONFIG_PS2KBD |
9b998b0c | 990 | puts("PS/2: "); |
1c43771b WD |
991 | kbd_init(); |
992 | #endif | |
993 | ||
4532cb69 | 994 | #ifdef CONFIG_MODEM_SUPPORT |
9b998b0c WD |
995 | { |
996 | extern int do_mdm_init; | |
997 | ||
998 | do_mdm_init = gd->do_mdm_init; | |
999 | } | |
4532cb69 WD |
1000 | #endif |
1001 | ||
fe8c2806 WD |
1002 | /* Initialization complete - start the monitor */ |
1003 | ||
1004 | /* main_loop() can return to retry autoboot, if so just run it again. */ | |
1005 | for (;;) { | |
9b998b0c WD |
1006 | WATCHDOG_RESET(); |
1007 | main_loop(); | |
fe8c2806 WD |
1008 | } |
1009 | ||
1010 | /* NOTREACHED - no way out of command loop except booting */ | |
1011 | } | |
1012 | ||
9b998b0c | 1013 | #if 0 /* We could use plain global data, but the resulting code is bigger */ |
fe8c2806 WD |
1014 | /* |
1015 | * Pointer to initial global data area | |
1016 | * | |
1017 | * Here we initialize it. | |
1018 | */ | |
1019 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
1020 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
9b998b0c WD |
1021 | DECLARE_GLOBAL_DATA_PTR = |
1022 | (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); | |
1023 | #endif /* 0 */ | |
fe8c2806 WD |
1024 | |
1025 | /************************************************************************/ |