projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| b02bad12 | 1 | /* |
| b55523ef | 2 | * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
| b02bad12 | 3 | * |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| b02bad12 NI |
5 | */ |
| 6 | ||
| 0b135cfc NI |
7 | #ifndef _ASM_CPU_SH4_H_ |
| 8 | #define _ASM_CPU_SH4_H_ | |
| b02bad12 NI |
9 | |
| 10 | /* cache control */ | |
| 11 | #define CCR_CACHE_STOP 0x00000808 | |
| 12 | #define CCR_CACHE_ENABLE 0x00000101 | |
| 13 | #define CCR_CACHE_ICI 0x00000800 | |
| 14 | ||
| 15 | #define CACHE_OC_ADDRESS_ARRAY 0xf4000000 | |
| c54b9a42 NI |
16 | |
| 17 | #if defined (CONFIG_CPU_SH7750) || \ | |
| 18 | defined(CONFIG_CPU_SH7751) | |
| b02bad12 NI |
19 | #define CACHE_OC_WAY_SHIFT 14 |
| 20 | #define CACHE_OC_NUM_ENTRIES 512 | |
| c54b9a42 NI |
21 | #else |
| 22 | #define CACHE_OC_WAY_SHIFT 13 | |
| 23 | #define CACHE_OC_NUM_ENTRIES 256 | |
| 24 | #endif | |
| b02bad12 | 25 | #define CACHE_OC_ENTRY_SHIFT 5 |
| b02bad12 | 26 | |
| 56693327 NI |
27 | #if defined (CONFIG_CPU_SH7750) || \ |
| 28 | defined(CONFIG_CPU_SH7751) | |
| 29 | # include <asm/cpu_sh7750.h> | |
| b02bad12 | 30 | #elif defined (CONFIG_CPU_SH7722) |
| 56693327 | 31 | # include <asm/cpu_sh7722.h> |
| ab09f433 NI |
32 | #elif defined (CONFIG_CPU_SH7723) |
| 33 | # include <asm/cpu_sh7723.h> | |
| bead86a8 NI |
34 | #elif defined (CONFIG_CPU_SH7724) |
| 35 | # include <asm/cpu_sh7724.h> | |
| 2a57e7ec NI |
36 | #elif defined (CONFIG_CPU_SH7734) |
| 37 | # include <asm/cpu_sh7734.h> | |
| 1a2621ba YS |
38 | #elif defined (CONFIG_CPU_SH7752) |
| 39 | # include <asm/cpu_sh7752.h> | |
| 8e9c897b YS |
40 | #elif defined (CONFIG_CPU_SH7757) |
| 41 | # include <asm/cpu_sh7757.h> | |
| 60179098 NI |
42 | #elif defined (CONFIG_CPU_SH7763) |
| 43 | # include <asm/cpu_sh7763.h> | |
| b55523ef | 44 | #elif defined (CONFIG_CPU_SH7780) |
| 56693327 | 45 | # include <asm/cpu_sh7780.h> |
| b0b62189 YS |
46 | #elif defined (CONFIG_CPU_SH7785) |
| 47 | # include <asm/cpu_sh7785.h> | |
| 0b135cfc | 48 | #else |
| 56693327 | 49 | # error "Unknown SH4 variant" |
| 0b135cfc | 50 | #endif |
| b02bad12 | 51 | |
| 6d84ae39 YS |
52 | #if defined(CONFIG_SH_32BIT) |
| 53 | #define PMB_ADDR_ARRAY 0xf6100000 | |
| 54 | #define PMB_ADDR_ENTRY 8 | |
| 55 | #define PMB_VPN 24 | |
| 56 | ||
| 57 | #define PMB_DATA_ARRAY 0xf7100000 | |
| 58 | #define PMB_DATA_ENTRY 8 | |
| 59 | #define PMB_PPN 24 | |
| 60 | #define PMB_UB 9 /* Buffered write */ | |
| 61 | #define PMB_V 8 /* Valid */ | |
| 62 | #define PMB_SZ1 7 /* Page size (upper bit) */ | |
| 63 | #define PMB_SZ0 4 /* Page size (lower bit) */ | |
| 64 | #define PMB_C 3 /* Cacheability */ | |
| 65 | #define PMB_WT 0 /* Write-through */ | |
| 66 | ||
| 67 | #define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY)) | |
| 68 | #define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY)) | |
| 69 | #define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN)) | |
| 70 | #define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \ | |
| 71 | ((ppn << PMB_PPN) | (ub << PMB_UB) | \ | |
| 72 | (v << PMB_V) | (sz1 << PMB_SZ1) | \ | |
| 73 | (sz0 << PMB_SZ0) | (c << PMB_C) | \ | |
| 74 | (wt << PMB_WT)) | |
| 75 | #endif | |
| 76 | ||
| b02bad12 | 77 | #endif /* _ASM_CPU_SH4_H_ */ |