projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c2f02da2 DH |
1 | /* SPARC I/O definitions |
| 2 | * | |
| 3 | * (C) Copyright 2007 | |
| 4 | * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License as | |
| 8 | * published by the Free Software Foundation; either version 2 of | |
| 9 | * the License, or (at your option) any later version. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU General Public License | |
| 17 | * along with this program; if not, write to the Free Software | |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 19 | * MA 02111-1307 USA | |
| 20 | * | |
| 21 | */ | |
| 22 | ||
| 23 | #ifndef _SPARC_IO_H | |
| 24 | #define _SPARC_IO_H | |
| 25 | ||
| 26 | /* Nothing to sync, total store ordering (TSO)... */ | |
| 27 | #define sync() | |
| 28 | ||
| 29 | /* Forces a cache miss on read/load. | |
| 30 | * On some architectures we need to bypass the cache when reading | |
| 31 | * I/O registers so that we are not reading the same status word | |
| 32 | * over and over again resulting in a hang (until an IRQ if lucky) | |
| 33 | * | |
| 34 | */ | |
| 6d0f6bcf | 35 | #ifndef CONFIG_SYS_HAS_NO_CACHE |
| c2f02da2 DH |
36 | #define READ_BYTE(var) SPARC_NOCACHE_READ_BYTE((unsigned int)(var)) |
| 37 | #define READ_HWORD(var) SPARC_NOCACHE_READ_HWORD((unsigned int)(var)) | |
| 38 | #define READ_WORD(var) SPARC_NOCACHE_READ((unsigned int)(var)) | |
| 39 | #define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)(var)) | |
| 40 | #else | |
| 41 | #define READ_BYTE(var) (var) | |
| 42 | #define READ_HWORD(var) (var) | |
| 43 | #define READ_WORD(var) (var) | |
| 44 | #define READ_DWORD(var) (var) | |
| 45 | #endif | |
| 46 | ||
| 47 | /* | |
| 48 | * Generic virtual read/write. | |
| 49 | */ | |
| 50 | #define __arch_getb(a) (READ_BYTE(a)) | |
| 51 | #define __arch_getw(a) (READ_HWORD(a)) | |
| 52 | #define __arch_getl(a) (READ_WORD(a)) | |
| 53 | #define __arch_getq(a) (READ_DWORD(a)) | |
| 54 | ||
| 55 | #define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) | |
| 56 | #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) | |
| 57 | #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) | |
| 58 | ||
| 59 | #define __raw_writeb(v,a) __arch_putb(v,a) | |
| 60 | #define __raw_writew(v,a) __arch_putw(v,a) | |
| 61 | #define __raw_writel(v,a) __arch_putl(v,a) | |
| 62 | ||
| 63 | #define __raw_readb(a) __arch_getb(a) | |
| 64 | #define __raw_readw(a) __arch_getw(a) | |
| 65 | #define __raw_readl(a) __arch_getl(a) | |
| 66 | #define __raw_readq(a) __arch_getq(a) | |
| 67 | ||
| 68 | /* | |
| 69 | * Given a physical address and a length, return a virtual address | |
| 70 | * that can be used to access the memory range with the caching | |
| 71 | * properties specified by "flags". | |
| 72 | */ | |
| c2f02da2 DH |
73 | |
| 74 | #define MAP_NOCACHE (0) | |
| 75 | #define MAP_WRCOMBINE (0) | |
| 76 | #define MAP_WRBACK (0) | |
| 77 | #define MAP_WRTHROUGH (0) | |
| 78 | ||
| 79 | static inline void *map_physmem(phys_addr_t paddr, unsigned long len, | |
| 80 | unsigned long flags) | |
| 81 | { | |
| 82 | return (void *)paddr; | |
| 83 | } | |
| 84 | ||
| 85 | /* | |
| 86 | * Take down a mapping set up by map_physmem(). | |
| 87 | */ | |
| 88 | static inline void unmap_physmem(void *vaddr, unsigned long flags) | |
| 89 | { | |
| 90 | ||
| 91 | } | |
| 92 | ||
| 65e43a10 KG |
93 | static inline phys_addr_t virt_to_phys(void * vaddr) |
| 94 | { | |
| 95 | return (phys_addr_t)(vaddr); | |
| 96 | } | |
| 97 | ||
| c2f02da2 | 98 | #endif |