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| Commit | Line | Data |
|---|---|---|
| c2f02da2 DH |
1 | /* SPARC Processor specifics |
| 2 | * taken from the SPARC port of Linux (ptrace.h). | |
| 3 | * | |
| 4 | * (C) Copyright 2007 | |
| 5 | * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. | |
| 6 | * | |
| 1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| c2f02da2 DH |
8 | */ |
| 9 | ||
| 10 | #ifndef __ASM_SPARC_PROCESSOR_H | |
| 11 | #define __ASM_SPARC_PROCESSOR_H | |
| 12 | ||
| 13 | #include <asm/arch/asi.h> | |
| 14 | ||
| 1e9a164e DH |
15 | #ifdef CONFIG_LEON |
| 16 | ||
| 17 | /* All LEON processors supported */ | |
| 18 | #include <asm/leon.h> | |
| 19 | ||
| 20 | #else | |
| 21 | /* other processors */ | |
| c2f02da2 | 22 | #error Unknown SPARC Processor |
| 1e9a164e | 23 | #endif |
| c2f02da2 DH |
24 | |
| 25 | #ifndef __ASSEMBLY__ | |
| 26 | ||
| 27 | /* flush data cache */ | |
| 28 | static __inline__ void sparc_dcache_flush_all(void) | |
| 29 | { | |
| 30 | __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory"); | |
| 31 | } | |
| 32 | ||
| 33 | /* flush instruction cache */ | |
| 34 | static __inline__ void sparc_icache_flush_all(void) | |
| 35 | { | |
| 36 | __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_IFLUSH):"memory"); | |
| 37 | } | |
| 38 | ||
| 39 | /* do a cache miss load */ | |
| 40 | static __inline__ unsigned long long sparc_load_reg_cachemiss_qword(unsigned | |
| 41 | long paddr) | |
| 42 | { | |
| 43 | unsigned long long retval; | |
| 44 | __asm__ __volatile__("ldda [%1] %2, %0\n\t": | |
| 45 | "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS)); | |
| 46 | return retval; | |
| 47 | } | |
| 48 | ||
| 49 | static __inline__ unsigned long sparc_load_reg_cachemiss(unsigned long paddr) | |
| 50 | { | |
| 51 | unsigned long retval; | |
| 52 | __asm__ __volatile__("lda [%1] %2, %0\n\t": | |
| 53 | "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS)); | |
| 54 | return retval; | |
| 55 | } | |
| 56 | ||
| 57 | static __inline__ unsigned short sparc_load_reg_cachemiss_word(unsigned long | |
| 58 | paddr) | |
| 59 | { | |
| 60 | unsigned short retval; | |
| 61 | __asm__ __volatile__("lduha [%1] %2, %0\n\t": | |
| 62 | "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS)); | |
| 63 | return retval; | |
| 64 | } | |
| 65 | ||
| 66 | static __inline__ unsigned char sparc_load_reg_cachemiss_byte(unsigned long | |
| 67 | paddr) | |
| 68 | { | |
| 69 | unsigned char retval; | |
| 70 | __asm__ __volatile__("lduba [%1] %2, %0\n\t": | |
| 71 | "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS)); | |
| 72 | return retval; | |
| 73 | } | |
| 74 | ||
| 75 | /* do a physical address bypass write, i.e. for 0x80000000 */ | |
| 76 | static __inline__ void sparc_store_reg_bypass(unsigned long paddr, | |
| 77 | unsigned long value) | |
| 78 | { | |
| 79 | __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(value), "r"(paddr), | |
| 80 | "i"(ASI_BYPASS):"memory"); | |
| 81 | } | |
| 82 | ||
| 83 | static __inline__ unsigned long sparc_load_reg_bypass(unsigned long paddr) | |
| 84 | { | |
| 85 | unsigned long retval; | |
| 86 | __asm__ __volatile__("lda [%1] %2, %0\n\t": | |
| 87 | "=r"(retval):"r"(paddr), "i"(ASI_BYPASS)); | |
| 88 | return retval; | |
| 89 | } | |
| 90 | ||
| 91 | /* Macros for bypassing cache when reading */ | |
| 92 | #define SPARC_NOCACHE_READ_DWORD(address) sparc_load_reg_cachemiss_qword((unsigned int)(address)) | |
| 93 | #define SPARC_NOCACHE_READ(address) sparc_load_reg_cachemiss((unsigned int)(address)) | |
| 94 | #define SPARC_NOCACHE_READ_HWORD(address) sparc_load_reg_cachemiss_word((unsigned int)(address)) | |
| 95 | #define SPARC_NOCACHE_READ_BYTE(address) sparc_load_reg_cachemiss_byte((unsigned int)(address)) | |
| 96 | ||
| 97 | #define SPARC_BYPASS_READ(address) sparc_load_reg_bypass((unsigned int)(address)) | |
| 98 | #define SPARC_BYPASS_WRITE(address,value) sparc_store_reg_bypass((unsigned int)(address),(unsigned int)(value)) | |
| 99 | ||
| 100 | #endif | |
| 101 | ||
| 102 | #endif /* __ASM_SPARC_PROCESSOR_H */ |