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Commit | Line | Data |
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3a1a18ff SG |
1 | # |
2 | # Copyright (C) 2015 Google, Inc | |
3 | # | |
4 | # SPDX-License-Identifier: GPL-2.0+ | |
5 | # | |
6 | ||
7 | config INTEL_BAYTRAIL | |
8 | bool | |
b4302582 | 9 | select HAVE_FSP if !EFI |
3612b1ef | 10 | select ARCH_MISC_INIT if !EFI |
81c727d8 | 11 | select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED |
1e452b46 | 12 | imply HAVE_INTEL_ME if !EFI |
67f99f97 | 13 | imply ENABLE_MRC_CACHE |
24357dfd | 14 | imply AHCI_PCI |
e88e1ef5 | 15 | imply ICH_SPI |
72436892 | 16 | imply INTEL_ICH6_GPIO |
e88e1ef5 BM |
17 | imply MMC |
18 | imply MMC_PCI | |
19 | imply MMC_SDHCI | |
20 | imply MMC_SDHCI_SDMA | |
21 | imply SCSI | |
9fd95ef0 | 22 | imply SCSI_AHCI |
e88e1ef5 BM |
23 | imply SPI_FLASH |
24 | imply SYS_NS16550 | |
b9342b2c BM |
25 | imply USB |
26 | imply USB_EHCI_HCD | |
27 | imply USB_XHCI_HCD | |
e88e1ef5 | 28 | imply VIDEO_VESA |
377656b2 BM |
29 | |
30 | if INTEL_BAYTRAIL | |
31 | config INTERNAL_UART | |
32 | bool "Enable the SoC integrated legacy UART" | |
33 | help | |
34 | There is a legacy UART integrated into the Bay Trail SoC. | |
35 | A maximum baud rate of 115200 bps is supported. For this | |
36 | reason, it is recommended that the UART port be used for | |
37 | debug purposes only, eg: U-Boot console. | |
38 | ||
37d10232 BM |
39 | config DEBUG_UART |
40 | bool | |
41 | select DEBUG_UART_BOARD_INIT | |
42 | ||
377656b2 | 43 | endif |