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ef5a5b00 GB |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2008 | |
4 | * Graeme Russ, graeme.russ@gmail.com. | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
ef5a5b00 GB |
7 | */ |
8 | ||
9 | #include <common.h> | |
10 | #include <asm/u-boot-x86.h> | |
11 | #include <flash.h> | |
12 | #include <netdev.h> | |
c78a62ac | 13 | #include <ns16550.h> |
17de114f SR |
14 | #include <asm/msr.h> |
15 | #include <asm/cache.h> | |
300081aa | 16 | #include <asm/io.h> |
63f559cd GB |
17 | #include <asm/arch-coreboot/tables.h> |
18 | #include <asm/arch-coreboot/sysinfo.h> | |
6dbe0cce | 19 | #include <asm/arch/timestamp.h> |
ef5a5b00 GB |
20 | |
21 | DECLARE_GLOBAL_DATA_PTR; | |
22 | ||
ef5a5b00 GB |
23 | /* |
24 | * Miscellaneous platform dependent initializations | |
25 | */ | |
63f559cd GB |
26 | int cpu_init_f(void) |
27 | { | |
28 | int ret = get_coreboot_info(&lib_sysinfo); | |
29 | if (ret != 0) | |
30 | printf("Failed to parse coreboot tables.\n"); | |
6dbe0cce VB |
31 | |
32 | timestamp_init(); | |
33 | ||
63f559cd GB |
34 | return ret; |
35 | } | |
36 | ||
ef5a5b00 GB |
37 | int board_early_init_f(void) |
38 | { | |
39 | return 0; | |
40 | } | |
41 | ||
42 | int board_early_init_r(void) | |
43 | { | |
44 | /* CPU Speed to 100MHz */ | |
45 | gd->cpu_clk = 100000000; | |
46 | ||
47 | /* Crystal is 33.000MHz */ | |
48 | gd->bus_clk = 33000000; | |
49 | ||
50 | return 0; | |
51 | } | |
52 | ||
53 | void show_boot_progress(int val) | |
54 | { | |
1350f1cc | 55 | #if MIN_PORT80_KCLOCKS_DELAY |
1350f1cc VB |
56 | /* |
57 | * Scale the time counter reading to avoid using 64 bit arithmetics. | |
58 | * Can't use get_timer() here becuase it could be not yet | |
59 | * initialized or even implemented. | |
60 | */ | |
bc2df1af SG |
61 | if (!gd->arch.tsc_prev) { |
62 | gd->arch.tsc_base_kclocks = rdtsc() / 1000; | |
63 | gd->arch.tsc_prev = 0; | |
1350f1cc VB |
64 | } else { |
65 | uint32_t now; | |
66 | ||
67 | do { | |
bc2df1af SG |
68 | now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; |
69 | } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); | |
70 | gd->arch.tsc_prev = now; | |
1350f1cc VB |
71 | } |
72 | #endif | |
300081aa | 73 | outb(val, 0x80); |
ef5a5b00 GB |
74 | } |
75 | ||
ef5a5b00 GB |
76 | int last_stage_init(void) |
77 | { | |
8f0278ea SG |
78 | if (gd->flags & GD_FLG_COLD_BOOT) |
79 | timestamp_add_to_bootstage(); | |
80 | ||
ef5a5b00 GB |
81 | return 0; |
82 | } | |
83 | ||
84 | #ifndef CONFIG_SYS_NO_FLASH | |
85 | ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) | |
86 | { | |
87 | return 0; | |
88 | } | |
89 | #endif | |
90 | ||
91 | int board_eth_init(bd_t *bis) | |
92 | { | |
93 | return pci_eth_init(bis); | |
94 | } | |
95 | ||
488b8b24 DL |
96 | #define MTRR_TYPE_WP 5 |
97 | #define MTRRcap_MSR 0xfe | |
17de114f SR |
98 | #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) |
99 | #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) | |
100 | ||
101 | int board_final_cleanup(void) | |
102 | { | |
103 | /* Un-cache the ROM so the kernel has one | |
104 | * more MTRR available. | |
488b8b24 DL |
105 | * |
106 | * Coreboot should have assigned this to the | |
107 | * top available variable MTRR. | |
17de114f | 108 | */ |
488b8b24 DL |
109 | u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1; |
110 | u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff; | |
111 | ||
112 | /* Make sure this MTRR is the correct Write-Protected type */ | |
113 | if (top_type == MTRR_TYPE_WP) { | |
114 | disable_caches(); | |
115 | wrmsrl(MTRRphysBase_MSR(top_mtrr), 0); | |
116 | wrmsrl(MTRRphysMask_MSR(top_mtrr), 0); | |
117 | enable_caches(); | |
118 | } | |
17de114f | 119 | |
b83058cd DL |
120 | /* Issue SMI to Coreboot to lock down ME and registers */ |
121 | printf("Finalizing Coreboot\n"); | |
122 | outb(0xcb, 0xb2); | |
123 | ||
17de114f SR |
124 | return 0; |
125 | } | |
c78a62ac SG |
126 | |
127 | void panic_puts(const char *str) | |
128 | { | |
129 | NS16550_t port = (NS16550_t)0x3f8; | |
130 | ||
131 | NS16550_init(port, 1); | |
132 | while (*str) | |
133 | NS16550_putc(port, *str++); | |
134 | } |