[people/ms/u-boot.git] / arch / x86 / cpu / ivybridge / sata.c

/*
 * From Coreboot
 * Copyright (C) 2008-2009 coresystems GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <ahci.h>
#include <dm.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/pch_common.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>

DECLARE_GLOBAL_DATA_PTR;

static void common_sata_init(struct udevice *dev, unsigned int port_map)
{
	u32 reg32;
	u16 reg16;

	/* Set IDE I/O Configuration */
	reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
	dm_pci_write_config32(dev, IDE_CONFIG, reg32);

	/* Port enable */
	dm_pci_read_config16(dev, 0x92, &reg16);
	reg16 &= ~0x3f;
	reg16 |= port_map;
	dm_pci_write_config16(dev, 0x92, reg16);

	/* SATA Initialization register */
	port_map &= 0xff;
	dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
}

static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
{
	unsigned int port_map, speed_support, port_tx;
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(dev);
	const char *mode;
	u32 reg32;
	u16 reg16;

	debug("SATA: Initializing...\n");

	/* SATA configuration */
	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
	speed_support = fdtdec_get_int(blob, node,
				       "sata_interface_speed_support", 0);

	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
	if (!mode || !strcmp(mode, "ahci")) {
		ulong abar;

		debug("SATA: Controller in AHCI mode\n");

		/* Set timings */
		dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
		dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);

		/* Sync DMA */
		dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
		dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);

		common_sata_init(dev, 0x8000 | port_map);

		/* Initialize AHCI memory-mapped space */
		abar = dm_pci_read_bar32(dev, 5);
		debug("ABAR: %08lx\n", abar);
		/* CAP (HBA Capabilities) : enable power management */
		reg32 = readl(abar + 0x00);
		reg32 |= 0x0c006000;  /* set PSC+SSC+SALP+SSS */
		reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
		/* Set ISS, if available */
		if (speed_support) {
			reg32 &= ~0x00f00000;
			reg32 |= (speed_support & 0x03) << 20;
		}
		writel(reg32, abar + 0x00);
		/* PI (Ports implemented) */
		writel(port_map, abar + 0x0c);
		(void) readl(abar + 0x0c); /* Read back 1 */
		(void) readl(abar + 0x0c); /* Read back 2 */
		/* CAP2 (HBA Capabilities Extended)*/
		reg32 = readl(abar + 0x24);
		reg32 &= ~0x00000002;
		writel(reg32, abar + 0x24);
		/* VSP (Vendor Specific Register */
		reg32 = readl(abar + 0xa0);
		reg32 &= ~0x00000005;
		writel(reg32, abar + 0xa0);
	} else if (!strcmp(mode, "combined")) {
		debug("SATA: Controller in combined mode\n");

		/* No AHCI: clear AHCI base */
		dm_pci_write_bar32(dev, 5, 0x00000000);
		/* And without AHCI BAR no memory decoding */
		dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
		reg16 &= ~PCI_COMMAND_MEMORY;
		dm_pci_write_config16(dev, PCI_COMMAND, reg16);

		dm_pci_write_config8(dev, 0x09, 0x80);

		/* Set timings */
		dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
		dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
				IDE_PPE0 | IDE_IE0 | IDE_TIME0);

		/* Sync DMA */
		dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
		dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);

		common_sata_init(dev, port_map);
	} else {
		debug("SATA: Controller in plain-ide mode\n");

		/* No AHCI: clear AHCI base */
		dm_pci_write_bar32(dev, 5, 0x00000000);

		/* And without AHCI BAR no memory decoding */
		dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
		reg16 &= ~PCI_COMMAND_MEMORY;
		dm_pci_write_config16(dev, PCI_COMMAND, reg16);

		/*
		 * Native mode capable on both primary and secondary (0xa)
		 * OR'ed with enabled (0x50) = 0xf
		 */
		dm_pci_write_config8(dev, 0x09, 0x8f);

		/* Set timings */
		dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
		dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
				IDE_SITRE | IDE_ISP_3_CLOCKS |
				IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);

		/* Sync DMA */
		dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
		dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);

		common_sata_init(dev, port_map);
	}

	/* Set Gen3 Transmitter settings if needed */
	port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
	if (port_tx)
		pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);

	port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
	if (port_tx)
		pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);

	/* Additional Programming Requirements */
	pch_common_sir_write(dev, 0x04, 0x00001600);
	pch_common_sir_write(dev, 0x28, 0xa0000033);
	reg32 = pch_common_sir_read(dev, 0x54);
	reg32 &= 0xff000000;
	reg32 |= 0x5555aa;
	pch_common_sir_write(dev, 0x54, reg32);
	pch_common_sir_write(dev, 0x64, 0xcccc8484);
	reg32 = pch_common_sir_read(dev, 0x68);
	reg32 &= 0xffff0000;
	reg32 |= 0xcccc;
	pch_common_sir_write(dev, 0x68, reg32);
	reg32 = pch_common_sir_read(dev, 0x78);
	reg32 &= 0x0000ffff;
	reg32 |= 0x88880000;
	pch_common_sir_write(dev, 0x78, reg32);
	pch_common_sir_write(dev, 0x84, 0x001c7000);
	pch_common_sir_write(dev, 0x88, 0x88338822);
	pch_common_sir_write(dev, 0xa0, 0x001c7000);
	pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
	pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
	pch_common_sir_write(dev, 0xd4, 0x10000000);

	pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
	pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
}

static void bd82x6x_sata_enable(struct udevice *dev)
{
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(dev);
	unsigned port_map;
	const char *mode;
	u16 map = 0;

	/*
	 * Set SATA controller mode early so the resource allocator can
	 * properly assign IO/Memory resources for the controller.
	 */
	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
	if (mode && !strcmp(mode, "ahci"))
		map = 0x0060;
	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);

	map |= (port_map ^ 0x3f) << 8;
	dm_pci_write_config16(dev, 0x90, map);
}

static int bd82x6x_sata_bind(struct udevice *dev)
{
	struct udevice *scsi_dev;
	int ret;

	if (gd->flags & GD_FLG_RELOC) {
		ret = ahci_bind_scsi(dev, &scsi_dev);
		if (ret)
			return ret;
	}

	return 0;
}

static int bd82x6x_sata_probe(struct udevice *dev)
{
	struct udevice *pch;
	int ret;

	ret = uclass_first_device_err(UCLASS_PCH, &pch);
	if (ret)
		return ret;

	if (!(gd->flags & GD_FLG_RELOC))
		bd82x6x_sata_enable(dev);
	else {
		bd82x6x_sata_init(dev, pch);
		ret = ahci_probe_scsi_pci(dev);
		if (ret)
			return ret;
	}

	return 0;
}

static const struct udevice_id bd82x6x_ahci_ids[] = {
	{ .compatible = "intel,pantherpoint-ahci" },
	{ }
};

U_BOOT_DRIVER(ahci_ivybridge_drv) = {
	.name		= "ahci_ivybridge",
	.id		= UCLASS_AHCI,
	.of_match	= bd82x6x_ahci_ids,
	.bind		= bd82x6x_sata_bind,
	.probe		= bd82x6x_sata_probe,
};
Commit	Line	Data
3ac83935 SG	1	/*
	2	* From Coreboot
	3	* Copyright (C) 2008-2009 coresystems GmbH
	4	*
	5	* SPDX-License-Identifier: GPL-2.0
	6	*/
	7
	8	#include <common.h>
32e9ec1f	9	#include <ahci.h>
d46f2a68	10	#include <dm.h>
3ac83935 SG	11	#include <fdtdec.h>
3ac83935 SG	12	#include <asm/io.h>
7e4a6ae6	13	#include <asm/pch_common.h>
3ac83935 SG	14	#include <asm/pci.h>
3ac83935 SG	15	#include <asm/arch/pch.h>
3ac83935	16
d46f2a68 SG	17	DECLARE_GLOBAL_DATA_PTR;
d46f2a68 SG	18
ddf10c20	19	static void common_sata_init(struct udevice *dev, unsigned int port_map)
3ac83935 SG	20	{
	21	u32 reg32;
	22	u16 reg16;
	23
	24	/* Set IDE I/O Configuration */
	25	reg32 = SIG_MODE_PRI_NORMAL \| FAST_PCB1 \| FAST_PCB0 \| PCB1 \| PCB0;
ddf10c20	26	dm_pci_write_config32(dev, IDE_CONFIG, reg32);
3ac83935 SG	27
3ac83935 SG	28	/* Port enable */
ddf10c20	29	dm_pci_read_config16(dev, 0x92, &reg16);
3ac83935 SG	30	reg16 &= ~0x3f;
3ac83935 SG	31	reg16 \|= port_map;
ddf10c20	32	dm_pci_write_config16(dev, 0x92, reg16);
3ac83935 SG	33
	34	/* SATA Initialization register */
	35	port_map &= 0xff;
ddf10c20	36	dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) \| 0x183);
3ac83935 SG	37	}
3ac83935 SG	38
9434c7a3	39	static void bd82x6x_sata_init(struct udevice dev, struct udevice pch)
3ac83935 SG	40	{
3ac83935 SG	41	unsigned int port_map, speed_support, port_tx;
ddf10c20	42	const void *blob = gd->fdt_blob;
e160f7d4	43	int node = dev_of_offset(dev);
3ac83935 SG	44	const char *mode;
	45	u32 reg32;
	46	u16 reg16;
	47
	48	debug("SATA: Initializing...\n");
	49
	50	/* SATA configuration */
	51	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
	52	speed_support = fdtdec_get_int(blob, node,
	53	"sata_interface_speed_support", 0);
	54
3ac83935 SG	55	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
3ac83935 SG	56	if (!mode \|\| !strcmp(mode, "ahci")) {
c7ccb2c0	57	ulong abar;
3ac83935 SG	58
	59	debug("SATA: Controller in AHCI mode\n");
	60
3ac83935	61	/* Set timings */
ddf10c20	62	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE \|
3ac83935 SG	63	IDE_ISP_3_CLOCKS \| IDE_RCT_1_CLOCKS \|
3ac83935 SG	64	IDE_PPE0 \| IDE_IE0 \| IDE_TIME0);
ddf10c20	65	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE \|
3ac83935 SG	66	IDE_ISP_5_CLOCKS \| IDE_RCT_4_CLOCKS);
	67
	68	/* Sync DMA */
ddf10c20 SG	69	dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
ddf10c20 SG	70	dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
3ac83935 SG	71
	72	common_sata_init(dev, 0x8000 \| port_map);
	73
	74	/* Initialize AHCI memory-mapped space */
ddf10c20	75	abar = dm_pci_read_bar32(dev, 5);
c7ccb2c0	76	debug("ABAR: %08lx\n", abar);
3ac83935 SG	77	/* CAP (HBA Capabilities) : enable power management */
	78	reg32 = readl(abar + 0x00);
	79	reg32 \|= 0x0c006000; /* set PSC+SSC+SALP+SSS */
	80	reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
	81	/* Set ISS, if available */
	82	if (speed_support) {
	83	reg32 &= ~0x00f00000;
	84	reg32 \|= (speed_support & 0x03) << 20;
	85	}
	86	writel(reg32, abar + 0x00);
	87	/* PI (Ports implemented) */
	88	writel(port_map, abar + 0x0c);
	89	(void) readl(abar + 0x0c); /* Read back 1 */
	90	(void) readl(abar + 0x0c); /* Read back 2 */
	91	/* CAP2 (HBA Capabilities Extended)*/
	92	reg32 = readl(abar + 0x24);
	93	reg32 &= ~0x00000002;
	94	writel(reg32, abar + 0x24);
	95	/* VSP (Vendor Specific Register */
	96	reg32 = readl(abar + 0xa0);
	97	reg32 &= ~0x00000005;
	98	writel(reg32, abar + 0xa0);
	99	} else if (!strcmp(mode, "combined")) {
	100	debug("SATA: Controller in combined mode\n");
	101
	102	/* No AHCI: clear AHCI base */
ddf10c20	103	dm_pci_write_bar32(dev, 5, 0x00000000);
3ac83935	104	/* And without AHCI BAR no memory decoding */
ddf10c20	105	dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
3ac83935	106	reg16 &= ~PCI_COMMAND_MEMORY;
ddf10c20	107	dm_pci_write_config16(dev, PCI_COMMAND, reg16);
3ac83935	108
ddf10c20	109	dm_pci_write_config8(dev, 0x09, 0x80);
3ac83935 SG	110
3ac83935 SG	111	/* Set timings */
ddf10c20	112	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE \|
3ac83935	113	IDE_ISP_5_CLOCKS \| IDE_RCT_4_CLOCKS);
ddf10c20	114	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE \|
3ac83935 SG	115	IDE_ISP_3_CLOCKS \| IDE_RCT_1_CLOCKS \|
	116	IDE_PPE0 \| IDE_IE0 \| IDE_TIME0);
	117
	118	/* Sync DMA */
ddf10c20 SG	119	dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
ddf10c20 SG	120	dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
3ac83935 SG	121
	122	common_sata_init(dev, port_map);
	123	} else {
	124	debug("SATA: Controller in plain-ide mode\n");
	125
	126	/* No AHCI: clear AHCI base */
ddf10c20	127	dm_pci_write_bar32(dev, 5, 0x00000000);
3ac83935 SG	128
3ac83935 SG	129	/* And without AHCI BAR no memory decoding */
ddf10c20	130	dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
3ac83935	131	reg16 &= ~PCI_COMMAND_MEMORY;
ddf10c20	132	dm_pci_write_config16(dev, PCI_COMMAND, reg16);
3ac83935 SG	133
	134	/*
	135	* Native mode capable on both primary and secondary (0xa)
	136	* OR'ed with enabled (0x50) = 0xf
	137	*/
ddf10c20	138	dm_pci_write_config8(dev, 0x09, 0x8f);
3ac83935 SG	139
3ac83935 SG	140	/* Set timings */
ddf10c20	141	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE \|
3ac83935 SG	142	IDE_ISP_3_CLOCKS \| IDE_RCT_1_CLOCKS \|
3ac83935 SG	143	IDE_PPE0 \| IDE_IE0 \| IDE_TIME0);
ddf10c20	144	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE \|
3ac83935 SG	145	IDE_SITRE \| IDE_ISP_3_CLOCKS \|
	146	IDE_RCT_1_CLOCKS \| IDE_IE0 \| IDE_TIME0);
	147
	148	/* Sync DMA */
ddf10c20 SG	149	dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 \| IDE_PSDE0);
ddf10c20 SG	150	dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
3ac83935 SG	151
	152	common_sata_init(dev, port_map);
	153	}
	154
	155	/* Set Gen3 Transmitter settings if needed */
	156	port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
	157	if (port_tx)
9434c7a3	158	pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);
3ac83935 SG	159
	160	port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
	161	if (port_tx)
9434c7a3	162	pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
3ac83935 SG	163
3ac83935 SG	164	/* Additional Programming Requirements */
7e4a6ae6 SG	165	pch_common_sir_write(dev, 0x04, 0x00001600);
	166	pch_common_sir_write(dev, 0x28, 0xa0000033);
	167	reg32 = pch_common_sir_read(dev, 0x54);
3ac83935 SG	168	reg32 &= 0xff000000;
3ac83935 SG	169	reg32 \|= 0x5555aa;
7e4a6ae6 SG	170	pch_common_sir_write(dev, 0x54, reg32);
	171	pch_common_sir_write(dev, 0x64, 0xcccc8484);
	172	reg32 = pch_common_sir_read(dev, 0x68);
3ac83935 SG	173	reg32 &= 0xffff0000;
3ac83935 SG	174	reg32 \|= 0xcccc;
7e4a6ae6 SG	175	pch_common_sir_write(dev, 0x68, reg32);
7e4a6ae6 SG	176	reg32 = pch_common_sir_read(dev, 0x78);
3ac83935 SG	177	reg32 &= 0x0000ffff;
3ac83935 SG	178	reg32 \|= 0x88880000;
7e4a6ae6 SG	179	pch_common_sir_write(dev, 0x78, reg32);
	180	pch_common_sir_write(dev, 0x84, 0x001c7000);
	181	pch_common_sir_write(dev, 0x88, 0x88338822);
	182	pch_common_sir_write(dev, 0xa0, 0x001c7000);
	183	pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
	184	pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
	185	pch_common_sir_write(dev, 0xd4, 0x10000000);
3ac83935	186
9434c7a3 SG	187	pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
9434c7a3 SG	188	pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
3ac83935 SG	189	}
3ac83935 SG	190
ddf10c20	191	static void bd82x6x_sata_enable(struct udevice *dev)
3ac83935	192	{
ddf10c20	193	const void *blob = gd->fdt_blob;
e160f7d4	194	int node = dev_of_offset(dev);
3ac83935 SG	195	unsigned port_map;
	196	const char *mode;
	197	u16 map = 0;
	198
	199	/*
	200	* Set SATA controller mode early so the resource allocator can
	201	* properly assign IO/Memory resources for the controller.
	202	*/
	203	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
	204	if (mode && !strcmp(mode, "ahci"))
	205	map = 0x0060;
	206	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
	207
	208	map \|= (port_map ^ 0x3f) << 8;
ddf10c20	209	dm_pci_write_config16(dev, 0x90, map);
3ac83935	210	}
d46f2a68	211
32e9ec1f SG	212	static int bd82x6x_sata_bind(struct udevice *dev)
	213	{
	214	struct udevice *scsi_dev;
	215	int ret;
	216
	217	if (gd->flags & GD_FLG_RELOC) {
	218	ret = ahci_bind_scsi(dev, &scsi_dev);
	219	if (ret)
	220	return ret;
	221	}
	222
	223	return 0;
	224	}
	225
d46f2a68 SG	226	static int bd82x6x_sata_probe(struct udevice *dev)
d46f2a68 SG	227	{
9434c7a3 SG	228	struct udevice *pch;
	229	int ret;
	230
3f603cbb	231	ret = uclass_first_device_err(UCLASS_PCH, &pch);
9434c7a3 SG	232	if (ret)
9434c7a3 SG	233	return ret;
9434c7a3	234
d46f2a68	235	if (!(gd->flags & GD_FLG_RELOC))
ddf10c20	236	bd82x6x_sata_enable(dev);
32e9ec1f	237	else {
9434c7a3	238	bd82x6x_sata_init(dev, pch);
745a94f3	239	ret = ahci_probe_scsi_pci(dev);
32e9ec1f SG	240	if (ret)
	241	return ret;
	242	}
d46f2a68 SG	243
	244	return 0;
	245	}
	246
	247	static const struct udevice_id bd82x6x_ahci_ids[] = {
	248	{ .compatible = "intel,pantherpoint-ahci" },
	249	{ }
	250	};
	251
	252	U_BOOT_DRIVER(ahci_ivybridge_drv) = {
	253	.name = "ahci_ivybridge",
a219639d	254	.id = UCLASS_AHCI,
d46f2a68	255	.of_match = bd82x6x_ahci_ids,
32e9ec1f	256	.bind = bd82x6x_sata_bind,
d46f2a68 SG	257	.probe = bd82x6x_sata_probe,
d46f2a68 SG	258	};