[people/ms/u-boot.git] / arch / x86 / cpu / quark / dram.c

/*
 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/post.h>
#include <asm/arch/mrc.h>
#include <asm/arch/msg_port.h>
#include <asm/arch/quark.h>

DECLARE_GLOBAL_DATA_PTR;

static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params)
{
	struct mrc_data_container *cache;
	struct mrc_region entry;
	int ret;

	ret = mrccache_get_region(NULL, &entry);
	if (ret)
		return ret;

	cache = mrccache_find_current(&entry);
	if (!cache)
		return -ENOENT;

	debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
	      cache->data, cache->data_size, cache->checksum);

	/* copy mrc cache to the mrc_params */
	memcpy(&mrc_params->timings, cache->data, cache->data_size);

	return 0;
}

static int mrc_configure_params(struct mrc_params *mrc_params)
{
	const void *blob = gd->fdt_blob;
	int node;
	int mrc_flags;

	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC);
	if (node < 0) {
		debug("%s: Cannot find MRC node\n", __func__);
		return -EINVAL;
	}

#ifdef CONFIG_ENABLE_MRC_CACHE
	mrc_params->boot_mode = prepare_mrc_cache(mrc_params);
	if (mrc_params->boot_mode)
		mrc_params->boot_mode = BM_COLD;
	else
		mrc_params->boot_mode = BM_FAST;
#else
	mrc_params->boot_mode = BM_COLD;
#endif

	/*
	 * TODO:
	 *
	 * We need determine ECC by pin strap state
	 *
	 * Disable ECC by default for now
	 */
	mrc_params->ecc_enables = 0;

	mrc_flags = fdtdec_get_int(blob, node, "flags", 0);
	if (mrc_flags & MRC_FLAG_SCRAMBLE_EN)
		mrc_params->scrambling_enables = 1;
	else
		mrc_params->scrambling_enables = 0;

	mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0);
	mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0);
	mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0);

	mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0);
	mrc_params->channel_enables = fdtdec_get_int(blob, node,
		"chan-mask", 0);
	mrc_params->channel_width = fdtdec_get_int(blob, node,
		"chan-width", 0);
	mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0);

	mrc_params->refresh_rate = fdtdec_get_int(blob, node,
		"refresh-rate", 0);
	mrc_params->sr_temp_range = fdtdec_get_int(blob, node,
		"sr-temp-range", 0);
	mrc_params->ron_value = fdtdec_get_int(blob, node,
		"ron-value", 0);
	mrc_params->rtt_nom_value = fdtdec_get_int(blob, node,
		"rtt-nom-value", 0);
	mrc_params->rd_odt_value = fdtdec_get_int(blob, node,
		"rd-odt-value", 0);

	mrc_params->params.density = fdtdec_get_int(blob, node,
		"dram-density", 0);
	mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0);
	mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0);
	mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0);
	mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0);
	mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0);

	debug("MRC dram_width %d\n", mrc_params->dram_width);
	debug("MRC rank_enables %d\n", mrc_params->rank_enables);
	debug("MRC ddr_speed %d\n", mrc_params->ddr_speed);
	debug("MRC flags: %s\n",
	      (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : "");

	debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
	      mrc_params->params.density, mrc_params->params.cl,
	      mrc_params->params.ras, mrc_params->params.wtr,
	      mrc_params->params.rrd, mrc_params->params.faw);

	return 0;
}

int dram_init(void)
{
	struct mrc_params mrc_params;
#ifdef CONFIG_ENABLE_MRC_CACHE
	char *cache;
#endif
	int ret;

	memset(&mrc_params, 0, sizeof(struct mrc_params));
	ret = mrc_configure_params(&mrc_params);
	if (ret)
		return ret;

	/* Set up the DRAM by calling the memory reference code */
	mrc_init(&mrc_params);
	if (mrc_params.status)
		return -EIO;

	gd->ram_size = mrc_params.mem_size;
	post_code(POST_DRAM);

	/* variable range MTRR#2: RAM area */
	disable_caches();
	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM),
		       0 | MTRR_TYPE_WRBACK);
	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM),
		       (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID);
	enable_caches();

#ifdef CONFIG_ENABLE_MRC_CACHE
	cache = malloc(sizeof(struct mrc_timings));
	if (cache) {
		memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings));
		gd->arch.mrc_output = cache;
		gd->arch.mrc_output_len = sizeof(struct mrc_timings);
	}
#endif

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = 0;
	gd->bd->bi_dram[0].size = gd->ram_size;

	return 0;
}

/*
 * This function looks for the highest region of memory lower than 4GB which
 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
 * It overrides the default implementation found elsewhere which simply
 * picks the end of ram, wherever that may be. The location of the stack,
 * the relocation address, and how far U-Boot is moved by relocation are
 * set in the global data structure.
 */
ulong board_get_usable_ram_top(ulong total_size)
{
	return gd->ram_size;
}
Commit	Line	Data
828d9af5 BM	1	/*
	2	* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
20c34115 BM	8	#include <errno.h>
20c34115 BM	9	#include <fdtdec.h>
2fc2b83a BM	10	#include <malloc.h>
2fc2b83a BM	11	#include <asm/mrccache.h>
c6d4705f	12	#include <asm/mtrr.h>
828d9af5	13	#include <asm/post.h>
20c34115	14	#include <asm/arch/mrc.h>
c6d4705f	15	#include <asm/arch/msg_port.h>
828d9af5 BM	16	#include <asm/arch/quark.h>
	17
	18	DECLARE_GLOBAL_DATA_PTR;
	19
2fc2b83a BM	20	static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params)
	21	{
	22	struct mrc_data_container *cache;
	23	struct mrc_region entry;
	24	int ret;
	25
	26	ret = mrccache_get_region(NULL, &entry);
	27	if (ret)
	28	return ret;
	29
	30	cache = mrccache_find_current(&entry);
	31	if (!cache)
	32	return -ENOENT;
	33
	34	debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
	35	cache->data, cache->data_size, cache->checksum);
	36
	37	/* copy mrc cache to the mrc_params */
	38	memcpy(&mrc_params->timings, cache->data, cache->data_size);
	39
	40	return 0;
	41	}
	42
20c34115 BM	43	static int mrc_configure_params(struct mrc_params *mrc_params)
	44	{
	45	const void *blob = gd->fdt_blob;
	46	int node;
	47	int mrc_flags;
	48
	49	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC);
	50	if (node < 0) {
	51	debug("%s: Cannot find MRC node\n", __func__);
	52	return -EINVAL;
	53	}
	54
2fc2b83a BM	55	#ifdef CONFIG_ENABLE_MRC_CACHE
	56	mrc_params->boot_mode = prepare_mrc_cache(mrc_params);
	57	if (mrc_params->boot_mode)
	58	mrc_params->boot_mode = BM_COLD;
	59	else
	60	mrc_params->boot_mode = BM_FAST;
	61	#else
20c34115	62	mrc_params->boot_mode = BM_COLD;
2fc2b83a	63	#endif
20c34115 BM	64
	65	/*
	66	* TODO:
	67	*
	68	* We need determine ECC by pin strap state
	69	*
	70	* Disable ECC by default for now
	71	*/
	72	mrc_params->ecc_enables = 0;
	73
	74	mrc_flags = fdtdec_get_int(blob, node, "flags", 0);
	75	if (mrc_flags & MRC_FLAG_SCRAMBLE_EN)
	76	mrc_params->scrambling_enables = 1;
	77	else
	78	mrc_params->scrambling_enables = 0;
	79
	80	mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0);
	81	mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0);
	82	mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0);
	83
	84	mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0);
	85	mrc_params->channel_enables = fdtdec_get_int(blob, node,
	86	"chan-mask", 0);
	87	mrc_params->channel_width = fdtdec_get_int(blob, node,
	88	"chan-width", 0);
	89	mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0);
	90
	91	mrc_params->refresh_rate = fdtdec_get_int(blob, node,
	92	"refresh-rate", 0);
	93	mrc_params->sr_temp_range = fdtdec_get_int(blob, node,
	94	"sr-temp-range", 0);
	95	mrc_params->ron_value = fdtdec_get_int(blob, node,
	96	"ron-value", 0);
	97	mrc_params->rtt_nom_value = fdtdec_get_int(blob, node,
	98	"rtt-nom-value", 0);
	99	mrc_params->rd_odt_value = fdtdec_get_int(blob, node,
	100	"rd-odt-value", 0);
	101
	102	mrc_params->params.density = fdtdec_get_int(blob, node,
	103	"dram-density", 0);
	104	mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0);
	105	mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0);
	106	mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0);
	107	mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0);
	108	mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0);
	109
	110	debug("MRC dram_width %d\n", mrc_params->dram_width);
	111	debug("MRC rank_enables %d\n", mrc_params->rank_enables);
	112	debug("MRC ddr_speed %d\n", mrc_params->ddr_speed);
	113	debug("MRC flags: %s\n",
	114	(mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : "");
	115
	116	debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
	117	mrc_params->params.density, mrc_params->params.cl,
	118	mrc_params->params.ras, mrc_params->params.wtr,
	119	mrc_params->params.rrd, mrc_params->params.faw);
	120
	121	return 0;
	122	}
	123
828d9af5 BM	124	int dram_init(void)
828d9af5 BM	125	{
20c34115	126	struct mrc_params mrc_params;
2fc2b83a BM	127	#ifdef CONFIG_ENABLE_MRC_CACHE
	128	char *cache;
	129	#endif
20c34115 BM	130	int ret;
	131
	132	memset(&mrc_params, 0, sizeof(struct mrc_params));
	133	ret = mrc_configure_params(&mrc_params);
	134	if (ret)
	135	return ret;
	136
	137	/* Set up the DRAM by calling the memory reference code */
	138	mrc_init(&mrc_params);
	139	if (mrc_params.status)
	140	return -EIO;
	141
	142	gd->ram_size = mrc_params.mem_size;
828d9af5 BM	143	post_code(POST_DRAM);
828d9af5 BM	144
c6d4705f BM	145	/* variable range MTRR#2: RAM area */
	146	disable_caches();
	147	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM),
	148	0 \| MTRR_TYPE_WRBACK);
	149	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM),
	150	(~(gd->ram_size - 1)) \| MTRR_PHYS_MASK_VALID);
	151	enable_caches();
	152
2fc2b83a BM	153	#ifdef CONFIG_ENABLE_MRC_CACHE
	154	cache = malloc(sizeof(struct mrc_timings));
	155	if (cache) {
	156	memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings));
	157	gd->arch.mrc_output = cache;
	158	gd->arch.mrc_output_len = sizeof(struct mrc_timings);
	159	}
	160	#endif
	161
828d9af5 BM	162	return 0;
	163	}
	164
76b00aca	165	int dram_init_banksize(void)
828d9af5 BM	166	{
	167	gd->bd->bi_dram[0].start = 0;
	168	gd->bd->bi_dram[0].size = gd->ram_size;
76b00aca SG	169
76b00aca SG	170	return 0;
828d9af5 BM	171	}
	172
	173	/*
	174	* This function looks for the highest region of memory lower than 4GB which
	175	* has enough space for U-Boot where U-Boot is aligned on a page boundary.
	176	* It overrides the default implementation found elsewhere which simply
	177	* picks the end of ram, wherever that may be. The location of the stack,
	178	* the relocation address, and how far U-Boot is moved by relocation are
	179	* set in the global data structure.
	180	*/
	181	ulong board_get_usable_ram_top(ulong total_size)
	182	{
	183	return gd->ram_size;
	184	}