[people/ms/u-boot.git] / arch / x86 / lib / fsp / fsp_dram.c

/*
 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/fsp/fsp_support.h>
#include <asm/e820.h>
#include <asm/mrccache.h>
#include <asm/post.h>

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	phys_size_t ram_size = 0;
	const struct hob_header *hdr;
	struct hob_res_desc *res_desc;

	hdr = gd->arch.hob_list;
	while (!end_of_hob(hdr)) {
		if (hdr->type == HOB_TYPE_RES_DESC) {
			res_desc = (struct hob_res_desc *)hdr;
			if (res_desc->type == RES_SYS_MEM ||
			    res_desc->type == RES_MEM_RESERVED) {
				ram_size += res_desc->len;
			}
		}
		hdr = get_next_hob(hdr);
	}

	gd->ram_size = ram_size;
	post_code(POST_DRAM);

#ifdef CONFIG_ENABLE_MRC_CACHE
	gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list,
					       &gd->arch.mrc_output_len);
#endif

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = 0;
	gd->bd->bi_dram[0].size = gd->ram_size;

	return 0;
}

/*
 * This function looks for the highest region of memory lower than 4GB which
 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
 * It overrides the default implementation found elsewhere which simply
 * picks the end of ram, wherever that may be. The location of the stack,
 * the relocation address, and how far U-Boot is moved by relocation are
 * set in the global data structure.
 */
ulong board_get_usable_ram_top(ulong total_size)
{
	return fsp_get_usable_lowmem_top(gd->arch.hob_list);
}

unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
{
	unsigned num_entries = 0;
	const struct hob_header *hdr;
	struct hob_res_desc *res_desc;

	hdr = gd->arch.hob_list;

	while (!end_of_hob(hdr)) {
		if (hdr->type == HOB_TYPE_RES_DESC) {
			res_desc = (struct hob_res_desc *)hdr;
			entries[num_entries].addr = res_desc->phys_start;
			entries[num_entries].size = res_desc->len;

			if (res_desc->type == RES_SYS_MEM)
				entries[num_entries].type = E820_RAM;
			else if (res_desc->type == RES_MEM_RESERVED)
				entries[num_entries].type = E820_RESERVED;

			num_entries++;
		}
		hdr = get_next_hob(hdr);
	}

	/* Mark PCIe ECAM address range as reserved */
	entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
	entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
	entries[num_entries].type = E820_RESERVED;
	num_entries++;

	return num_entries;
}
Commit	Line	Data
b2e02d28 BM	1	/*
	2	* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
1021af4d	8	#include <asm/fsp/fsp_support.h>
b2e02d28	9	#include <asm/e820.h>
ff1e18af	10	#include <asm/mrccache.h>
b2e02d28 BM	11	#include <asm/post.h>
	12
	13	DECLARE_GLOBAL_DATA_PTR;
	14
	15	int dram_init(void)
	16	{
	17	phys_size_t ram_size = 0;
949dbc12 BM	18	const struct hob_header *hdr;
949dbc12 BM	19	struct hob_res_desc *res_desc;
b2e02d28	20
949dbc12 BM	21	hdr = gd->arch.hob_list;
949dbc12 BM	22	while (!end_of_hob(hdr)) {
b2439aec	23	if (hdr->type == HOB_TYPE_RES_DESC) {
949dbc12 BM	24	res_desc = (struct hob_res_desc *)hdr;
	25	if (res_desc->type == RES_SYS_MEM \|\|
	26	res_desc->type == RES_MEM_RESERVED) {
	27	ram_size += res_desc->len;
b2e02d28 BM	28	}
b2e02d28 BM	29	}
949dbc12	30	hdr = get_next_hob(hdr);
b2e02d28 BM	31	}
	32
	33	gd->ram_size = ram_size;
	34	post_code(POST_DRAM);
	35
ff1e18af BM	36	#ifdef CONFIG_ENABLE_MRC_CACHE
	37	gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list,
	38	&gd->arch.mrc_output_len);
	39	#endif
	40
b2e02d28 BM	41	return 0;
	42	}
	43
76b00aca	44	int dram_init_banksize(void)
b2e02d28 BM	45	{
	46	gd->bd->bi_dram[0].start = 0;
	47	gd->bd->bi_dram[0].size = gd->ram_size;
76b00aca SG	48
76b00aca SG	49	return 0;
b2e02d28 BM	50	}
	51
	52	/*
	53	* This function looks for the highest region of memory lower than 4GB which
	54	* has enough space for U-Boot where U-Boot is aligned on a page boundary.
	55	* It overrides the default implementation found elsewhere which simply
	56	* picks the end of ram, wherever that may be. The location of the stack,
	57	* the relocation address, and how far U-Boot is moved by relocation are
	58	* set in the global data structure.
	59	*/
	60	ulong board_get_usable_ram_top(ulong total_size)
	61	{
255fd5ca	62	return fsp_get_usable_lowmem_top(gd->arch.hob_list);
b2e02d28 BM	63	}
	64
	65	unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
	66	{
	67	unsigned num_entries = 0;
949dbc12 BM	68	const struct hob_header *hdr;
949dbc12 BM	69	struct hob_res_desc *res_desc;
b2e02d28	70
949dbc12	71	hdr = gd->arch.hob_list;
b2e02d28	72
949dbc12	73	while (!end_of_hob(hdr)) {
b2439aec	74	if (hdr->type == HOB_TYPE_RES_DESC) {
949dbc12 BM	75	res_desc = (struct hob_res_desc *)hdr;
	76	entries[num_entries].addr = res_desc->phys_start;
	77	entries[num_entries].size = res_desc->len;
b2e02d28	78
949dbc12	79	if (res_desc->type == RES_SYS_MEM)
b2e02d28	80	entries[num_entries].type = E820_RAM;
949dbc12	81	else if (res_desc->type == RES_MEM_RESERVED)
b2e02d28	82	entries[num_entries].type = E820_RESERVED;
196193a4 BM	83
196193a4 BM	84	num_entries++;
b2e02d28	85	}
949dbc12	86	hdr = get_next_hob(hdr);
b2e02d28 BM	87	}
b2e02d28 BM	88
1ed6648b BM	89	/* Mark PCIe ECAM address range as reserved */
	90	entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
	91	entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
	92	entries[num_entries].type = E820_RESERVED;
	93	num_entries++;
	94
b2e02d28 BM	95	return num_entries;
b2e02d28 BM	96	}