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1 | /* |
2 | * Copyright 2013-2015 Arcturus Networks, Inc | |
3 | * http://www.arcturusnetworks.com/products/ucp1020/ | |
4 | * based on board/freescale/p1_p2_rdb_pc/tlb.c | |
5 | * original copyright follows: | |
6 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | #include <common.h> | |
12 | #include <asm/mmu.h> | |
13 | ||
14 | struct fsl_e_tlb_entry tlb_table[] = { | |
15 | /* TLB 0 - for temp stack in cache */ | |
16 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, | |
17 | CONFIG_SYS_INIT_RAM_ADDR_PHYS, | |
18 | MAS3_SX | MAS3_SW | MAS3_SR, 0, | |
19 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
20 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, | |
21 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, | |
22 | MAS3_SX | MAS3_SW | MAS3_SR, 0, | |
23 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
24 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, | |
25 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, | |
26 | MAS3_SX | MAS3_SW | MAS3_SR, 0, | |
27 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
28 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, | |
29 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, | |
30 | MAS3_SX | MAS3_SW | MAS3_SR, 0, | |
31 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
32 | ||
33 | /* TLB 1 */ | |
34 | /* *I*** - Covers boot page */ | |
35 | SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, | |
36 | MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, | |
37 | 0, 0, BOOKE_PAGESZ_4K, 1), | |
38 | ||
39 | /* *I*G* - CCSRBAR */ | |
40 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, | |
41 | MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, | |
42 | 0, 1, BOOKE_PAGESZ_1M, 1), | |
43 | ||
44 | #ifndef CONFIG_SPL_BUILD | |
45 | /* W**G* - Flash/promjet, localbus */ | |
46 | /* This will be changed to *I*G* after relocation to RAM. */ | |
47 | SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, | |
48 | MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, | |
49 | 0, 2, BOOKE_PAGESZ_64M, 1), | |
50 | ||
51 | #ifdef CONFIG_PCI | |
52 | /* *I*G* - PCI memory 1.5G */ | |
53 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, | |
54 | MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, | |
55 | 0, 3, BOOKE_PAGESZ_1G, 1), | |
56 | ||
57 | /* *I*G* - PCI I/O effective: 192K */ | |
58 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, | |
59 | MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, | |
60 | 0, 4, BOOKE_PAGESZ_256K, 1), | |
61 | #endif | |
62 | ||
63 | #ifdef CONFIG_VSC7385_ENET | |
64 | /* *I*G - VSC7385 Switch */ | |
65 | SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, | |
66 | MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, | |
67 | 0, 5, BOOKE_PAGESZ_1M, 1), | |
68 | #endif | |
69 | #endif /* not SPL */ | |
70 | ||
71 | #ifdef CONFIG_SYS_NAND_BASE | |
72 | /* *I*G - NAND */ | |
73 | SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, | |
74 | MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, | |
75 | 0, 7, BOOKE_PAGESZ_1M, 1), | |
76 | #endif | |
77 | ||
78 | #if defined(CONFIG_SYS_RAMBOOT) || \ | |
79 | (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) | |
80 | /* *I*G - eSDHC/eSPI/NAND boot */ | |
81 | SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, | |
316f0d0f | 82 | MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, |
8b0044ff OZ |
83 | 0, 8, BOOKE_PAGESZ_1G, 1), |
84 | ||
85 | #endif /* RAMBOOT/SPL */ | |
86 | ||
87 | #ifdef CONFIG_SYS_INIT_L2_ADDR | |
88 | /* *I*G - L2SRAM */ | |
89 | SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, | |
90 | MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G, | |
91 | 0, 11, BOOKE_PAGESZ_256K, 1), | |
92 | #if CONFIG_SYS_L2_SIZE >= (256 << 10) | |
93 | SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, | |
94 | CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, | |
95 | MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, | |
96 | 0, 12, BOOKE_PAGESZ_256K, 1) | |
97 | #endif | |
98 | #endif | |
99 | }; | |
100 | ||
101 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |