[people/ms/u-boot.git] / board / BuS / EB+MCF-EV123 / EB+MCF-EV123.c

/*
 * (C) Copyright 2005
 * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include "asm/m5282.h"
#include "VCxK.h"

int checkboard (void)
{
	puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
#if (TEXT_BASE ==  CONFIG_SYS_INT_FLASH_BASE)
	puts ("       Boot from Internal FLASH\n");
#endif

	return 0;
}

phys_size_t initdram (int board_type)
{
	int size, i;

	size = 0;
	MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
			| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
#ifdef CONFIG_SYS_SDRAM_BASE0

	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
			| MCFSDRAMC_DACR_CASL (1)
			| MCFSDRAMC_DACR_CBM (3)
			| MCFSDRAMC_DACR_PS_16;

	MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;

	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;

	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
	for (i = 0; i < 2000; i++)
		asm (" nop");
	mbar_writeLong (MCFSDRAMC_DACR0,
			mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
	size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
#ifdef CONFIG_SYS_SDRAM_BASE1
	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
			| MCFSDRAMC_DACR_CASL (1)
			| MCFSDRAMC_DACR_CBM (3)
			| MCFSDRAMC_DACR_PS_16;

	MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;

	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;

	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;

	for (i = 0; i < 2000; i++)
		asm (" nop");

	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
#endif
	return size;
}


#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test passed.\n");
	return 0;
}
#endif

int misc_init_r(void)
{
	init_vcxk();
	return 1;
}

/*---------------------------------------------------------------------------*/

int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	int rcode = 0;
	ulong source;

	switch (argc) {
	case 2:
		source = simple_strtoul(argv[1],NULL,16);
		vcxk_loadimage(source);
		rcode = 0;
		break;
	default:
		cmd_usage(cmdtp);
		rcode = 1;
		break;
	}
	return rcode;
}

/***************************************************/

U_BOOT_CMD(
	vcimage,	2,	0,	do_vcimage,
	"vcimage - loads an image to Display\n",
	"vcimage addr\n"
);

/* EOF EB+MCF-EV123c */
Commit	Line	Data
9acb626f HS	1	/*
	2	* (C) Copyright 2005
	3	* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
	4	*
	5	* (C) Copyright 2000-2003
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <command.h>
	29	#include "asm/m5282.h"
	30	#include "VCxK.h"
	31
	32	int checkboard (void)
	33	{
	34	puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
6d0f6bcf	35	#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
9acb626f HS	36	puts (" Boot from Internal FLASH\n");
	37	#endif
	38
	39	return 0;
	40	}
	41
9973e3c6	42	phys_size_t initdram (int board_type)
9acb626f	43	{
0fe34058	44	int size, i;
9acb626f HS	45
9acb626f HS	46	size = 0;
0fe34058	47	MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
6d0f6bcf JCPV	48	\| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
6d0f6bcf JCPV	49	#ifdef CONFIG_SYS_SDRAM_BASE0
0fe34058	50
6d0f6bcf	51	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
0fe34058 WD	52	\| MCFSDRAMC_DACR_CASL (1)
	53	\| MCFSDRAMC_DACR_CBM (3)
	54	\| MCFSDRAMC_DACR_PS_16;
	55
	56	MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M \| MCFSDRAMC_DMR_V;
	57
	58	MCFSDRAMC_DACR0 \|= MCFSDRAMC_DACR_IP;
	59
6d0f6bcf	60	(unsigned short ) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
0fe34058 WD	61	MCFSDRAMC_DACR0 \|= MCFSDRAMC_DACR_RE;
	62	for (i = 0; i < 2000; i++)
	63	asm (" nop");
	64	mbar_writeLong (MCFSDRAMC_DACR0,
	65	mbar_readLong (MCFSDRAMC_DACR0) \| MCFSDRAMC_DACR_IMRS);
6d0f6bcf JCPV	66	(unsigned int ) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
6d0f6bcf JCPV	67	size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
0fe34058	68	#endif
6d0f6bcf JCPV	69	#ifdef CONFIG_SYS_SDRAM_BASE1
6d0f6bcf JCPV	70	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
0fe34058 WD	71	\| MCFSDRAMC_DACR_CASL (1)
	72	\| MCFSDRAMC_DACR_CBM (3)
	73	\| MCFSDRAMC_DACR_PS_16;
	74
	75	MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M \| MCFSDRAMC_DMR_V;
	76
	77	MCFSDRAMC_DACR1 \|= MCFSDRAMC_DACR_IP;
	78
6d0f6bcf	79	(unsigned short ) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
0fe34058 WD	80	MCFSDRAMC_DACR1 \|= MCFSDRAMC_DACR_RE;
	81
	82	for (i = 0; i < 2000; i++)
	83	asm (" nop");
	84
	85	MCFSDRAMC_DACR1 \|= MCFSDRAMC_DACR_IMRS;
6d0f6bcf JCPV	86	(unsigned int ) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
6d0f6bcf JCPV	87	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
0fe34058	88	#endif
9acb626f HS	89	return size;
	90	}
	91
	92
6d0f6bcf	93	#if defined(CONFIG_SYS_DRAM_TEST)
9acb626f HS	94	int testdram (void)
9acb626f HS	95	{
6d0f6bcf JCPV	96	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	97	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
9acb626f HS	98	uint *p;
	99
	100	printf("SDRAM test phase 1:\n");
	101	for (p = pstart; p < pend; p++)
	102	*p = 0xaaaaaaaa;
	103
	104	for (p = pstart; p < pend; p++) {
	105	if (*p != 0xaaaaaaaa) {
	106	printf ("SDRAM test fails at: %08x\n", (uint) p);
	107	return 1;
	108	}
	109	}
	110
	111	printf("SDRAM test phase 2:\n");
	112	for (p = pstart; p < pend; p++)
	113	*p = 0x55555555;
	114
	115	for (p = pstart; p < pend; p++) {
	116	if (*p != 0x55555555) {
	117	printf ("SDRAM test fails at: %08x\n", (uint) p);
	118	return 1;
	119	}
	120	}
	121
	122	printf("SDRAM test passed.\n");
	123	return 0;
	124	}
	125	#endif
	126
	127	int misc_init_r(void)
	128	{
	129	init_vcxk();
	130	return 1;
	131	}
	132
	133	/---------------------------------------------------------------------------/
	134
	135	int do_vcimage (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	136	{
	137	int rcode = 0;
	138	ulong source;
	139
	140	switch (argc) {
	141	case 2:
	142	source = simple_strtoul(argv[1],NULL,16);
	143	vcxk_loadimage(source);
	144	rcode = 0;
	145	break;
	146	default:
62c3ae7c	147	cmd_usage(cmdtp);
9acb626f HS	148	rcode = 1;
	149	break;
	150	}
	151	return rcode;
	152	}
	153
	154	/***************************************************/
	155
	156	U_BOOT_CMD(
	157	vcimage, 2, 0, do_vcimage,
	158	"vcimage - loads an image to Display\n",
	159	"vcimage addr\n"
	160	);
	161
	162	/* EOF EB+MCF-EV123c */