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1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Net Insight <www.netinsight.net> | |
4 | * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> | |
5 | * | |
6 | * Based on sheevaplug.c: | |
7 | * (C) Copyright 2009 | |
8 | * Marvell Semiconductor <www.marvell.com> | |
9 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
10 | * | |
1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
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12 | */ |
13 | ||
14 | #include <common.h> | |
15 | #include <miiphy.h> | |
a7efd719 | 16 | #include <asm/arch/cpu.h> |
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17 | #include <asm/arch/kirkwood.h> |
18 | #include <asm/arch/mpp.h> | |
f846604f | 19 | #include "openrd.h" |
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20 | |
21 | DECLARE_GLOBAL_DATA_PTR; | |
22 | ||
754ae3fb | 23 | int board_early_init_f(void) |
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24 | { |
25 | /* | |
26 | * default gpio configuration | |
27 | * There are maximum 64 gpios controlled through 2 sets of registers | |
28 | * the below configuration configures mainly initial LED status | |
29 | */ | |
30 | kw_config_gpio(OPENRD_OE_VAL_LOW, | |
31 | OPENRD_OE_VAL_HIGH, | |
32 | OPENRD_OE_LOW, OPENRD_OE_HIGH); | |
33 | ||
34 | /* Multi-Purpose Pins Functionality configuration */ | |
9d86f0c3 | 35 | static const u32 kwmpp_config[] = { |
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36 | MPP0_NF_IO2, |
37 | MPP1_NF_IO3, | |
38 | MPP2_NF_IO4, | |
39 | MPP3_NF_IO5, | |
40 | MPP4_NF_IO6, | |
41 | MPP5_NF_IO7, | |
42 | MPP6_SYSRST_OUTn, | |
43 | MPP7_GPO, | |
44 | MPP8_TW_SDA, | |
45 | MPP9_TW_SCK, | |
46 | MPP10_UART0_TXD, | |
47 | MPP11_UART0_RXD, | |
48 | MPP12_SD_CLK, | |
49 | MPP13_SD_CMD, /* Alt UART1_TXD */ | |
50 | MPP14_SD_D0, /* Alt UART1_RXD */ | |
51 | MPP15_SD_D1, | |
52 | MPP16_SD_D2, | |
53 | MPP17_SD_D3, | |
54 | MPP18_NF_IO0, | |
55 | MPP19_NF_IO1, | |
56 | MPP20_GE1_0, | |
57 | MPP21_GE1_1, | |
58 | MPP22_GE1_2, | |
59 | MPP23_GE1_3, | |
60 | MPP24_GE1_4, | |
61 | MPP25_GE1_5, | |
62 | MPP26_GE1_6, | |
63 | MPP27_GE1_7, | |
64 | MPP28_GPIO, | |
65 | MPP29_TSMP9, | |
66 | MPP30_GE1_10, | |
67 | MPP31_GE1_11, | |
68 | MPP32_GE1_12, | |
69 | MPP33_GE1_13, | |
70 | MPP34_GPIO, /* UART1 / SD sel */ | |
71 | MPP35_TDM_CH0_TX_QL, | |
72 | MPP36_TDM_SPI_CS1, | |
73 | MPP37_TDM_CH2_TX_QL, | |
74 | MPP38_TDM_CH2_RX_QL, | |
75 | MPP39_AUDIO_I2SBCLK, | |
76 | MPP40_AUDIO_I2SDO, | |
77 | MPP41_AUDIO_I2SLRC, | |
78 | MPP42_AUDIO_I2SMCLK, | |
79 | MPP43_AUDIO_I2SDI, | |
80 | MPP44_AUDIO_EXTCLK, | |
81 | MPP45_TDM_PCLK, | |
82 | MPP46_TDM_FS, | |
83 | MPP47_TDM_DRX, | |
84 | MPP48_TDM_DTX, | |
85 | MPP49_TDM_CH0_RX_QL, | |
86 | 0 | |
87 | }; | |
88 | ||
84683638 | 89 | kirkwood_mpp_conf(kwmpp_config, NULL); |
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90 | return 0; |
91 | } | |
e92daeb5 | 92 | |
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93 | int board_init(void) |
94 | { | |
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95 | /* |
96 | * arch number of board | |
97 | */ | |
21861f2d | 98 | #if defined(CONFIG_BOARD_IS_OPENRD_BASE) |
e92daeb5 | 99 | gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; |
21861f2d CA |
100 | #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) |
101 | gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; | |
102 | #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) | |
103 | gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; | |
104 | #endif | |
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105 | |
106 | /* adress of boot parameters */ | |
107 | gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; | |
108 | return 0; | |
109 | } | |
110 | ||
e92daeb5 | 111 | #ifdef CONFIG_RESET_PHY_R |
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112 | /* Configure and enable MV88E1116/88E1121 PHY */ |
113 | void mv_phy_init(char *name) | |
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114 | { |
115 | u16 reg; | |
116 | u16 devadr; | |
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117 | |
118 | if (miiphy_set_current_dev(name)) | |
119 | return; | |
120 | ||
121 | /* command to read PHY dev address */ | |
122 | if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { | |
123 | printf("Err..%s could not read PHY dev address\n", | |
124 | __FUNCTION__); | |
125 | return; | |
126 | } | |
127 | ||
128 | /* | |
129 | * Enable RGMII delay on Tx and Rx for CPU port | |
130 | * Ref: sec 4.7.2 of chip datasheet | |
131 | */ | |
132 | miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); | |
133 | miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); | |
134 | reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); | |
135 | miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); | |
136 | miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); | |
137 | ||
138 | /* reset the phy */ | |
139 | miiphy_reset(name, devadr); | |
140 | ||
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141 | printf(PHY_NO" Initialized on %s\n", name); |
142 | } | |
143 | ||
144 | void reset_phy(void) | |
145 | { | |
146 | mv_phy_init("egiga0"); | |
147 | ||
148 | #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT | |
149 | /* Kirkwood ethernet driver is written with the assumption that in case | |
150 | * of multiple PHYs, their addresses are consecutive. But unfortunately | |
151 | * in case of OpenRD-Client, PHY addresses are not consecutive.*/ | |
152 | miiphy_write("egiga1", 0xEE, 0xEE, 24); | |
153 | #endif | |
154 | ||
155 | #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ | |
156 | defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) | |
157 | /* configure and initialize both PHY's */ | |
158 | mv_phy_init("egiga1"); | |
159 | #endif | |
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160 | } |
161 | #endif /* CONFIG_RESET_PHY_R */ |