[people/ms/u-boot.git] / board / Marvell / sheevaplug / sheevaplug.c

/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <miiphy.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include "sheevaplug.h"

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	/*
	 * default gpio configuration
	 * There are maximum 64 gpios controlled through 2 sets of registers
	 * the  below configuration configures mainly initial LED status
	 */
	mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
			  SHEEVAPLUG_OE_VAL_HIGH,
			  SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);

	/* Multi-Purpose Pins Functionality configuration */
	static const u32 kwmpp_config[] = {
		MPP0_NF_IO2,
		MPP1_NF_IO3,
		MPP2_NF_IO4,
		MPP3_NF_IO5,
		MPP4_NF_IO6,
		MPP5_NF_IO7,
		MPP6_SYSRST_OUTn,
		MPP7_GPO,
		MPP8_UART0_RTS,
		MPP9_UART0_CTS,
		MPP10_UART0_TXD,
		MPP11_UART0_RXD,
		MPP12_SD_CLK,
		MPP13_SD_CMD,
		MPP14_SD_D0,
		MPP15_SD_D1,
		MPP16_SD_D2,
		MPP17_SD_D3,
		MPP18_NF_IO0,
		MPP19_NF_IO1,
		MPP20_GPIO,
		MPP21_GPIO,
		MPP22_GPIO,
		MPP23_GPIO,
		MPP24_GPIO,
		MPP25_GPIO,
		MPP26_GPIO,
		MPP27_GPIO,
		MPP28_GPIO,
		MPP29_TSMP9,
		MPP30_GPIO,
		MPP31_GPIO,
		MPP32_GPIO,
		MPP33_GPIO,
		MPP34_GPIO,
		MPP35_GPIO,
		MPP36_GPIO,
		MPP37_GPIO,
		MPP38_GPIO,
		MPP39_GPIO,
		MPP40_GPIO,
		MPP41_GPIO,
		MPP42_GPIO,
		MPP43_GPIO,
		MPP44_GPIO,
		MPP45_GPIO,
		MPP46_GPIO,
		MPP47_GPIO,
		MPP48_GPIO,
		MPP49_GPIO,
		0
	};
	kirkwood_mpp_conf(kwmpp_config, NULL);
	return 0;
}

int board_init(void)
{
	/*
	 * arch number of board
	 */
	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
	u16 reg;
	u16 devadr;
	char *name = "egiga0";

	if (miiphy_set_current_dev(name))
		return;

	/* command to read PHY dev address */
	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
		printf("Err..%s could not read PHY dev address\n",
			__FUNCTION__);
		return;
	}

	/*
	 * Enable RGMII delay on Tx and Rx for CPU port
	 * Ref: sec 4.7.2 of chip datasheet
	 */
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);

	/* reset the phy */
	miiphy_reset(name, devadr);

	printf("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_RESET_PHY_R */
Commit	Line	Data
55dd4ba5 PW	1	/*
	2	* (C) Copyright 2009
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
55dd4ba5 PW	7	*/
	8
	9	#include <common.h>
	10	#include <miiphy.h>
c62db35d	11	#include <asm/mach-types.h>
a7efd719	12	#include <asm/arch/cpu.h>
3dc23f78	13	#include <asm/arch/soc.h>
55dd4ba5 PW	14	#include <asm/arch/mpp.h>
	15	#include "sheevaplug.h"
	16
	17	DECLARE_GLOBAL_DATA_PTR;
	18
754ae3fb	19	int board_early_init_f(void)
55dd4ba5 PW	20	{
	21	/*
	22	* default gpio configuration
	23	* There are maximum 64 gpios controlled through 2 sets of registers
	24	* the below configuration configures mainly initial LED status
	25	*/
d5c5132f SR	26	mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
	27	SHEEVAPLUG_OE_VAL_HIGH,
	28	SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
55dd4ba5 PW	29
55dd4ba5 PW	30	/* Multi-Purpose Pins Functionality configuration */
9d86f0c3	31	static const u32 kwmpp_config[] = {
55dd4ba5 PW	32	MPP0_NF_IO2,
	33	MPP1_NF_IO3,
	34	MPP2_NF_IO4,
	35	MPP3_NF_IO5,
	36	MPP4_NF_IO6,
	37	MPP5_NF_IO7,
	38	MPP6_SYSRST_OUTn,
	39	MPP7_GPO,
	40	MPP8_UART0_RTS,
	41	MPP9_UART0_CTS,
	42	MPP10_UART0_TXD,
	43	MPP11_UART0_RXD,
	44	MPP12_SD_CLK,
	45	MPP13_SD_CMD,
	46	MPP14_SD_D0,
	47	MPP15_SD_D1,
	48	MPP16_SD_D2,
	49	MPP17_SD_D3,
	50	MPP18_NF_IO0,
	51	MPP19_NF_IO1,
	52	MPP20_GPIO,
	53	MPP21_GPIO,
	54	MPP22_GPIO,
	55	MPP23_GPIO,
	56	MPP24_GPIO,
	57	MPP25_GPIO,
	58	MPP26_GPIO,
	59	MPP27_GPIO,
	60	MPP28_GPIO,
	61	MPP29_TSMP9,
	62	MPP30_GPIO,
	63	MPP31_GPIO,
	64	MPP32_GPIO,
	65	MPP33_GPIO,
	66	MPP34_GPIO,
	67	MPP35_GPIO,
	68	MPP36_GPIO,
	69	MPP37_GPIO,
	70	MPP38_GPIO,
	71	MPP39_GPIO,
	72	MPP40_GPIO,
	73	MPP41_GPIO,
	74	MPP42_GPIO,
	75	MPP43_GPIO,
	76	MPP44_GPIO,
	77	MPP45_GPIO,
	78	MPP46_GPIO,
	79	MPP47_GPIO,
	80	MPP48_GPIO,
	81	MPP49_GPIO,
	82	0
	83	};
84683638	84	kirkwood_mpp_conf(kwmpp_config, NULL);
754ae3fb PW	85	return 0;
754ae3fb PW	86	}
55dd4ba5	87
754ae3fb PW	88	int board_init(void)
754ae3fb PW	89	{
55dd4ba5 PW	90	/*
	91	* arch number of board
	92	*/
	93	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
	94
	95	/* adress of boot parameters */
96c5f081	96	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
55dd4ba5 PW	97
	98	return 0;
	99	}
	100
55dd4ba5 PW	101	#ifdef CONFIG_RESET_PHY_R
	102	/* Configure and enable MV88E1116 PHY */
	103	void reset_phy(void)
	104	{
	105	u16 reg;
	106	u16 devadr;
	107	char *name = "egiga0";
	108
	109	if (miiphy_set_current_dev(name))
	110	return;
	111
	112	/* command to read PHY dev address */
	113	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
	114	printf("Err..%s could not read PHY dev address\n",
	115	__FUNCTION__);
	116	return;
	117	}
	118
	119	/*
	120	* Enable RGMII delay on Tx and Rx for CPU port
	121	* Ref: sec 4.7.2 of chip datasheet
	122	*/
	123	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	124	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
	125	reg \|= (MV88E1116_RGMII_RXTM_CTRL \| MV88E1116_RGMII_TXTM_CTRL);
	126	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
	127	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
	128
	129	/* reset the phy */
	130	miiphy_reset(name, devadr);
	131
	132	printf("88E1116 Initialized on %s\n", name);
	133	}
	134	#endif /* CONFIG_RESET_PHY_R */