[people/ms/u-boot.git] / board / Seagate / goflexhome / goflexhome.c

/*
 * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
 *
 * Based on dockstar.c originally written by
 * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
 *
 * Based on sheevaplug.c originally written by
 * Prafulla Wadaskar <prafulla@marvell.com>
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <miiphy.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/arch/cpu.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	/* Multi-Purpose Pins Functionality configuration */
	static const u32 kwmpp_config[] = {
		MPP0_NF_IO2,
		MPP1_NF_IO3,
		MPP2_NF_IO4,
		MPP3_NF_IO5,
		MPP4_NF_IO6,
		MPP5_NF_IO7,
		MPP6_SYSRST_OUTn,
		MPP7_GPO,
		MPP8_UART0_RTS,
		MPP9_UART0_CTS,
		MPP10_UART0_TXD,
		MPP11_UART0_RXD,
		MPP12_SD_CLK,
		MPP13_SD_CMD,
		MPP14_SD_D0,
		MPP15_SD_D1,
		MPP16_SD_D2,
		MPP17_SD_D3,
		MPP18_NF_IO0,
		MPP19_NF_IO1,
		MPP20_GPIO,
		MPP21_GPIO,
		MPP22_GPIO,
		MPP23_GPIO,
		MPP24_GPIO,
		MPP25_GPIO,
		MPP26_GPIO,
		MPP27_GPIO,
		MPP28_GPIO,
		MPP29_TSMP9,
		MPP30_GPIO,
		MPP31_GPIO,
		MPP32_GPIO,
		MPP33_GPIO,
		MPP34_GPIO,
		MPP35_GPIO,
		MPP36_GPIO,
		MPP37_GPIO,
		MPP38_GPIO,
		MPP39_GPIO,
		MPP40_GPIO,
		MPP41_GPIO,
		MPP42_GPIO,
		MPP43_GPIO,
		MPP44_GPIO,
		MPP45_GPIO,
		MPP46_GPIO,
		MPP47_GPIO,
		MPP48_GPIO,
		MPP49_GPIO,
		0
	};

	/*
	 * default gpio configuration
	 * There are maximum 64 gpios controlled through 2 sets of registers
	 * the  below configuration configures mainly initial LED status
	 */
	mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
			  GOFLEXHOME_OE_VAL_HIGH,
			  GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
	kirkwood_mpp_conf(kwmpp_config, NULL);
	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
	u16 reg;
	u16 devadr;
	char *name = "egiga0";

	if (miiphy_set_current_dev(name))
		return;

	/* command to read PHY dev address */
	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
		printf("Err..%s could not read PHY dev address\n",
		       __func__);
		return;
	}

	/*
	 * Enable RGMII delay on Tx and Rx for CPU port
	 * Ref: sec 4.7.2 of chip datasheet
	 */
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);

	/* reset the phy */
	miiphy_reset(name, devadr);

	printf("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_RESET_PHY_R */

#define GREEN_LED	(1 << 14)
#define ORANGE_LED	(1 << 15)
#define BOTH_LEDS	(GREEN_LED | ORANGE_LED)
#define NEITHER_LED	0

static void set_leds(u32 leds, u32 blinking)
{
	struct kwgpio_registers *r;
	u32 oe;
	u32 bl;

	r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
	oe = readl(&r->oe) | BOTH_LEDS;
	writel(oe & ~leds, &r->oe);	/* active low */
	bl = readl(&r->blink_en) & ~BOTH_LEDS;
	writel(bl | blinking, &r->blink_en);
}

void show_boot_progress(int val)
{
	switch (val) {
	case BOOTSTAGE_ID_RUN_OS:		/* booting Linux */
		set_leds(BOTH_LEDS, NEITHER_LED);
		break;
	case BOOTSTAGE_ID_NET_ETH_START:	/* Ethernet initialization */
		set_leds(GREEN_LED, GREEN_LED);
		break;
	default:
		if (val < 0)	/* error */
			set_leds(ORANGE_LED, ORANGE_LED);
		break;
	}
}
Commit	Line	Data
0ad6c34c SR	1	/*
	2	* Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
	3	*
	4	* Based on dockstar.c originally written by
	5	* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
	6	*
	7	* Based on sheevaplug.c originally written by
	8	* Prafulla Wadaskar <prafulla@marvell.com>
	9	* (C) Copyright 2009
	10	* Marvell Semiconductor <www.marvell.com>
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
0ad6c34c SR	13	*/
	14
	15	#include <common.h>
	16	#include <miiphy.h>
3dc23f78	17	#include <asm/arch/soc.h>
0ad6c34c SR	18	#include <asm/arch/mpp.h>
	19	#include <asm/arch/cpu.h>
	20	#include <asm/io.h>
	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
	24	int board_early_init_f(void)
	25	{
	26	/* Multi-Purpose Pins Functionality configuration */
	27	static const u32 kwmpp_config[] = {
	28	MPP0_NF_IO2,
	29	MPP1_NF_IO3,
	30	MPP2_NF_IO4,
	31	MPP3_NF_IO5,
	32	MPP4_NF_IO6,
	33	MPP5_NF_IO7,
	34	MPP6_SYSRST_OUTn,
	35	MPP7_GPO,
	36	MPP8_UART0_RTS,
	37	MPP9_UART0_CTS,
	38	MPP10_UART0_TXD,
	39	MPP11_UART0_RXD,
	40	MPP12_SD_CLK,
	41	MPP13_SD_CMD,
	42	MPP14_SD_D0,
	43	MPP15_SD_D1,
	44	MPP16_SD_D2,
	45	MPP17_SD_D3,
	46	MPP18_NF_IO0,
	47	MPP19_NF_IO1,
	48	MPP20_GPIO,
	49	MPP21_GPIO,
	50	MPP22_GPIO,
	51	MPP23_GPIO,
	52	MPP24_GPIO,
	53	MPP25_GPIO,
	54	MPP26_GPIO,
	55	MPP27_GPIO,
	56	MPP28_GPIO,
	57	MPP29_TSMP9,
	58	MPP30_GPIO,
	59	MPP31_GPIO,
	60	MPP32_GPIO,
	61	MPP33_GPIO,
	62	MPP34_GPIO,
	63	MPP35_GPIO,
	64	MPP36_GPIO,
	65	MPP37_GPIO,
	66	MPP38_GPIO,
	67	MPP39_GPIO,
	68	MPP40_GPIO,
	69	MPP41_GPIO,
	70	MPP42_GPIO,
	71	MPP43_GPIO,
	72	MPP44_GPIO,
	73	MPP45_GPIO,
	74	MPP46_GPIO,
	75	MPP47_GPIO,
	76	MPP48_GPIO,
	77	MPP49_GPIO,
	78	0
	79	};
	80
	81	/*
82	* default gpio configuration
83	* There are maximum 64 gpios controlled through 2 sets of registers
84	* the below configuration configures mainly initial LED status
85	*/
d5c5132f SR	86	mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
	87	GOFLEXHOME_OE_VAL_HIGH,
	88	GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
0ad6c34c SR	89	kirkwood_mpp_conf(kwmpp_config, NULL);
	90	return 0;
	91	}
	92
	93	int board_init(void)
	94	{
0ad6c34c	95	/* address of boot parameters */
96c5f081	96	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
0ad6c34c SR	97
	98	return 0;
	99	}
	100
	101	#ifdef CONFIG_RESET_PHY_R
	102	/* Configure and enable MV88E1116 PHY */
	103	void reset_phy(void)
	104	{
	105	u16 reg;
	106	u16 devadr;
	107	char *name = "egiga0";
	108
	109	if (miiphy_set_current_dev(name))
	110	return;
	111
	112	/* command to read PHY dev address */
	113	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
	114	printf("Err..%s could not read PHY dev address\n",
	115	__func__);
	116	return;
	117	}
	118
	119	/*
	120	* Enable RGMII delay on Tx and Rx for CPU port
	121	* Ref: sec 4.7.2 of chip datasheet
	122	*/
	123	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	124	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
	125	reg \|= (MV88E1116_RGMII_RXTM_CTRL \| MV88E1116_RGMII_TXTM_CTRL);
	126	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
	127	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
	128
	129	/* reset the phy */
	130	miiphy_reset(name, devadr);
	131
	132	printf("88E1116 Initialized on %s\n", name);
	133	}
	134	#endif /* CONFIG_RESET_PHY_R */
	135
	136	#define GREEN_LED (1 << 14)
	137	#define ORANGE_LED (1 << 15)
	138	#define BOTH_LEDS (GREEN_LED \| ORANGE_LED)
	139	#define NEITHER_LED 0
	140
	141	static void set_leds(u32 leds, u32 blinking)
	142	{
	143	struct kwgpio_registers *r;
	144	u32 oe;
	145	u32 bl;
	146
d5c5132f	147	r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
0ad6c34c SR	148	oe = readl(&r->oe) \| BOTH_LEDS;
	149	writel(oe & ~leds, &r->oe); /* active low */
	150	bl = readl(&r->blink_en) & ~BOTH_LEDS;
	151	writel(bl \| blinking, &r->blink_en);
	152	}
	153
	154	void show_boot_progress(int val)
	155	{
	156	switch (val) {
	157	case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
	158	set_leds(BOTH_LEDS, NEITHER_LED);
	159	break;
	160	case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
	161	set_leds(GREEN_LED, GREEN_LED);
	162	break;
	163	default:
	164	if (val < 0) /* error */
	165	set_leds(ORANGE_LED, ORANGE_LED);
	166	break;
	167	}
	168	}