[people/ms/u-boot.git] / board / a3000 / a3000.c

/*
 * (C) Copyright 2001
 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
 *
 * Modified during 2003 by
 * Ken Chou, kchou@ieee.org
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc824x.h>
#include <pci.h>
#include <netdev.h>

int checkboard (void)
{
	ulong busfreq  = get_bus_freq(0);
	char  buf[32];

	printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq));
	return 0;

}

phys_size_t initdram (int board_type)
{
	long size;
	long new_bank0_end;
	long mear1;
	long emear1;

	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);

	new_bank0_end = size - 1;
	mear1 = mpc824x_mpc107_getreg(MEAR1);
	emear1 = mpc824x_mpc107_getreg(EMEAR1);
	mear1 = (mear1  & 0xFFFFFF00) |
		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
	emear1 = (emear1 & 0xFFFFFF00) |
		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
	mpc824x_mpc107_setreg(MEAR1, mear1);
	mpc824x_mpc107_setreg(EMEAR1, emear1);

	return (size);
}

/*
 * Initialize PCI Devices
 */
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_a3000_config_table[] = {
	/* vendor, device, class */
	/* bus, dev, func */
	{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
	  PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,	/* dp83815 eth0 divice */
	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
				       PCI_ENET0_MEMADDR,
				       PCI_COMMAND_IO |
				       PCI_COMMAND_MEMORY |
				       PCI_COMMAND_MASTER }},
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  PCI_ANY_ID, 0x14, PCI_ANY_ID,		/* PCI slot1 */
	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
				       PCI_ENET1_MEMADDR,
				       PCI_COMMAND_IO |
				       PCI_COMMAND_MEMORY |
				       PCI_COMMAND_MASTER }},
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  PCI_ANY_ID, 0x15, PCI_ANY_ID,		/* PCI slot2 */
	  pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
				       PCI_ENET2_MEMADDR,
				       PCI_COMMAND_IO |
				       PCI_COMMAND_MEMORY |
				       PCI_COMMAND_MASTER }},
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  PCI_ANY_ID, 0x16, PCI_ANY_ID,		/* PCI slot3 */
	  pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
				       PCI_ENET3_MEMADDR,
				       PCI_COMMAND_IO |
				       PCI_COMMAND_MEMORY |
				       PCI_COMMAND_MASTER }},
	{ }
};
#endif

struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_a3000_config_table,
#endif
};

void pci_init_board(void)
{
	pci_mpc824x_init(&hose);
}

int board_eth_init(bd_t *bis)
{
	return pci_eth_init(bis);
}
Commit	Line	Data
0332990b WD	1	/*
	2	* (C) Copyright 2001
	3	* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
	4	*
8564acf9 WD	5	* Modified during 2003 by
	6	* Ken Chou, kchou@ieee.org
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
0332990b WD	9	*/
	10
	11	#include <common.h>
	12	#include <mpc824x.h>
	13	#include <pci.h>
b902b8dd	14	#include <netdev.h>
0332990b WD	15
	16	int checkboard (void)
	17	{
	18	ulong busfreq = get_bus_freq(0);
	19	char buf[32];
	20
	21	printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq));
	22	return 0;
	23
	24	}
	25
9973e3c6	26	phys_size_t initdram (int board_type)
0332990b	27	{
c83bf6a2 WD	28	long size;
	29	long new_bank0_end;
	30	long mear1;
	31	long emear1;
0332990b	32
6d0f6bcf	33	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
0332990b	34
c83bf6a2 WD	35	new_bank0_end = size - 1;
	36	mear1 = mpc824x_mpc107_getreg(MEAR1);
	37	emear1 = mpc824x_mpc107_getreg(EMEAR1);
	38	mear1 = (mear1 & 0xFFFFFF00) \|
	39	((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
	40	emear1 = (emear1 & 0xFFFFFF00) \|
	41	((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
	42	mpc824x_mpc107_setreg(MEAR1, mear1);
	43	mpc824x_mpc107_setreg(EMEAR1, emear1);
0332990b	44
c83bf6a2	45	return (size);
0332990b WD	46	}
	47
	48	/*
	49	* Initialize PCI Devices
	50	*/
0332990b WD	51	#ifndef CONFIG_PCI_PNP
0332990b WD	52	static struct pci_config_table pci_a3000_config_table[] = {
945af8d7 WD	53	/* vendor, device, class */
945af8d7 WD	54	/* bus, dev, func */
8564acf9	55	{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
945af8d7	56	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */
0332990b WD	57	pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
	58	PCI_ENET0_MEMADDR,
	59	PCI_COMMAND_IO \|
	60	PCI_COMMAND_MEMORY \|
	61	PCI_COMMAND_MASTER }},
	62	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
945af8d7	63	PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */
0332990b WD	64	pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
	65	PCI_ENET1_MEMADDR,
	66	PCI_COMMAND_IO \|
	67	PCI_COMMAND_MEMORY \|
	68	PCI_COMMAND_MASTER }},
	69	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
53677ef1	70	PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */
0332990b WD	71	pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
	72	PCI_ENET2_MEMADDR,
	73	PCI_COMMAND_IO \|
	74	PCI_COMMAND_MEMORY \|
	75	PCI_COMMAND_MASTER }},
8564acf9	76	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
945af8d7	77	PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */
8564acf9 WD	78	pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
	79	PCI_ENET3_MEMADDR,
	80	PCI_COMMAND_IO \|
	81	PCI_COMMAND_MEMORY \|
	82	PCI_COMMAND_MASTER }},
0332990b WD	83	{ }
	84	};
	85	#endif
	86
0332990b WD	87	struct pci_controller hose = {
	88	#ifndef CONFIG_PCI_PNP
	89	config_table: pci_a3000_config_table,
	90	#endif
	91	};
	92
	93	void pci_init_board(void)
	94	{
	95	pci_mpc824x_init(&hose);
	96	}
b902b8dd BW	97
	98	int board_eth_init(bd_t *bis)
	99	{
	100	return pci_eth_init(bis);
	101	}