projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 3da42859 DN |
1 | /* |
| 2 | * Copyright Altera Corporation (C) 2012-2015 | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: BSD-3-Clause | |
| 5 | */ | |
| 6 | ||
| 7 | ||
| 8 | #define RW_MGR_READ_B2B_WAIT2 0x6A | |
| 9 | #define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31 | |
| 10 | #define RW_MGR_REFRESH_ALL 0x14 | |
| 11 | #define RW_MGR_ZQCL 0x06 | |
| 12 | #define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22 | |
| 13 | #define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23 | |
| 14 | #define RW_MGR_ACTIVATE_0_AND_1 0x0D | |
| 15 | #define RW_MGR_MRS2_MIRR 0x0A | |
| 16 | #define RW_MGR_INIT_RESET_0_CKE_0 0x6E | |
| 17 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45 | |
| 18 | #define RW_MGR_ACTIVATE_1 0x0F | |
| 19 | #define RW_MGR_MRS2 0x04 | |
| 20 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34 | |
| 21 | #define RW_MGR_MRS1 0x03 | |
| 3da42859 | 22 | #define RW_MGR_IDLE_LOOP1 0x7A |
| 3da42859 DN |
23 | #define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18 |
| 24 | #define RW_MGR_MRS3 0x05 | |
| 3da42859 | 25 | #define RW_MGR_IDLE_LOOP2 0x79 |
| 3da42859 DN |
26 | #define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E |
| 27 | #define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24 | |
| 28 | #define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C | |
| 3da42859 | 29 | #define RW_MGR_RDIMM_CMD 0x78 |
| 3da42859 DN |
30 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36 |
| 31 | #define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A | |
| 32 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38 | |
| 33 | #define RW_MGR_GUARANTEED_READ_CONT 0x53 | |
| 34 | #define RW_MGR_MRS3_MIRR 0x0B | |
| 35 | #define RW_MGR_IDLE 0x00 | |
| 36 | #define RW_MGR_READ_B2B 0x58 | |
| 37 | #define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F | |
| 38 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37 | |
| 39 | #define RW_MGR_GUARANTEED_WRITE 0x17 | |
| 40 | #define RW_MGR_PRECHARGE_ALL 0x12 | |
| 41 | #define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74 | |
| 3da42859 | 42 | #define RW_MGR_SGLE_READ 0x7C |
| 3da42859 DN |
43 | #define RW_MGR_MRS0_USER_MIRR 0x0C |
| 44 | #define RW_MGR_RETURN 0x01 | |
| 45 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35 | |
| 46 | #define RW_MGR_MRS0_USER 0x07 | |
| 47 | #define RW_MGR_GUARANTEED_READ 0x4B | |
| 48 | #define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 | |
| 49 | #define RW_MGR_INIT_RESET_1_CKE_0 0x73 | |
| 50 | #define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 | |
| 51 | #define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20 | |
| 52 | #define RW_MGR_MRS0_DLL_RESET 0x02 | |
| 53 | #define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E | |
| 54 | #define RW_MGR_LFSR_WR_RD_BANK_0 0x21 | |
| 55 | #define RW_MGR_CLEAR_DQS_ENABLE 0x48 | |
| 56 | #define RW_MGR_MRS1_MIRR 0x09 | |
| 57 | #define RW_MGR_READ_B2B_WAIT1 0x60 | |
| 58 | #define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680 | |
| 59 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680 | |
| 60 | #define RW_MGR_CONTENT_REFRESH_ALL 0x000980 | |
| 61 | #define RW_MGR_CONTENT_ZQCL 0x008380 | |
| 62 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700 | |
| 63 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00 | |
| 64 | #define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800 | |
| 65 | #define RW_MGR_CONTENT_MRS2_MIRR 0x008580 | |
| 66 | #define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000 | |
| 67 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680 | |
| 68 | #define RW_MGR_CONTENT_ACTIVATE_1 0x000880 | |
| 69 | #define RW_MGR_CONTENT_MRS2 0x008280 | |
| 70 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00 | |
| 71 | #define RW_MGR_CONTENT_MRS1 0x008200 | |
| 72 | #define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680 | |
| 73 | #define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8 | |
| 74 | #define RW_MGR_CONTENT_MRS3 0x008300 | |
| 75 | #define RW_MGR_CONTENT_IDLE_LOOP2 0x008680 | |
| 76 | #define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88 | |
| 77 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0 | |
| 78 | #define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88 | |
| 79 | #define RW_MGR_CONTENT_RDIMM_CMD 0x009180 | |
| 80 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700 | |
| 81 | #define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8 | |
| 82 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0 | |
| 83 | #define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168 | |
| 84 | #define RW_MGR_CONTENT_MRS3_MIRR 0x008600 | |
| 85 | #define RW_MGR_CONTENT_IDLE 0x080000 | |
| 86 | #define RW_MGR_CONTENT_READ_B2B 0x040E88 | |
| 87 | #define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000 | |
| 88 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00 | |
| 89 | #define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68 | |
| 90 | #define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900 | |
| 91 | #define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080 | |
| 92 | #define RW_MGR_CONTENT_SGLE_READ 0x040F08 | |
| 93 | #define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400 | |
| 94 | #define RW_MGR_CONTENT_RETURN 0x080680 | |
| 95 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80 | |
| 96 | #define RW_MGR_CONTENT_MRS0_USER 0x008100 | |
| 97 | #define RW_MGR_CONTENT_GUARANTEED_READ 0x001168 | |
| 98 | #define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480 | |
| 99 | #define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080 | |
| 100 | #define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680 | |
| 101 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00 | |
| 102 | #define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180 | |
| 103 | #define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680 | |
| 104 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80 | |
| 105 | #define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158 | |
| 106 | #define RW_MGR_CONTENT_MRS1_MIRR 0x008500 | |
| 107 | #define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680 | |
| 108 |