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3da42859 DN |
1 | /* |
2 | * Copyright Altera Corporation (C) 2012-2015 | |
3 | * | |
4 | * SPDX-License-Identifier: BSD-3-Clause | |
5 | */ | |
6 | ||
7 | #ifndef _SEQUENCER_DEFINES_H_ | |
8 | #define _SEQUENCER_DEFINES_H_ | |
9 | ||
10 | #define AC_ROM_MR1_MIRR 0000000000100 | |
11 | #define AC_ROM_MR1_OCD_ENABLE | |
12 | #define AC_ROM_MR2_MIRR 0000000010000 | |
13 | #define AC_ROM_MR3_MIRR 0000000000000 | |
14 | #define AC_ROM_MR0_CALIB | |
3da42859 DN |
15 | #define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000 |
16 | #define AC_ROM_MR0_DLL_RESET 0100100110000 | |
17 | #define AC_ROM_MR0_MIRR 0100001001001 | |
18 | #define AC_ROM_MR0 0100000110001 | |
3da42859 DN |
19 | #define AC_ROM_MR1 0000000000100 |
20 | #define AC_ROM_MR2 0000000001000 | |
21 | #define AC_ROM_MR3 0000000000000 | |
3da42859 | 22 | #define AFI_CLK_FREQ 534 |
3da42859 DN |
23 | #define AFI_RATE_RATIO 1 |
24 | #define AVL_CLK_FREQ 67 | |
25 | #define BFM_MODE 0 | |
26 | #define BURST2 0 | |
3da42859 DN |
27 | #define CALIB_LFIFO_OFFSET 8 |
28 | #define CALIB_VFIFO_OFFSET 6 | |
3da42859 DN |
29 | #define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 |
30 | #define ENABLE_SUPER_QUICK_CALIBRATION 0 | |
31 | #define GUARANTEED_READ_BRINGUP_TEST 0 | |
32 | #define HARD_PHY 1 | |
33 | #define HARD_VFIFO 1 | |
34 | #define HPS_HW 1 | |
35 | #define HR_DDIO_OUT_HAS_THREE_REGS 0 | |
36 | #define IO_DELAY_PER_DCHAIN_TAP 25 | |
37 | #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 | |
3da42859 | 38 | #define IO_DELAY_PER_OPA_TAP 234 |
3da42859 DN |
39 | #define IO_DLL_CHAIN_LENGTH 8 |
40 | #define IO_DM_OUT_RESERVE 0 | |
41 | #define IO_DQDQS_OUT_PHASE_MAX 0 | |
3da42859 DN |
42 | #define IO_DQS_EN_DELAY_MAX 15 |
43 | #define IO_DQS_EN_DELAY_OFFSET 16 | |
3da42859 DN |
44 | #define IO_DQS_EN_PHASE_MAX 7 |
45 | #define IO_DQS_IN_DELAY_MAX 31 | |
46 | #define IO_DQS_IN_RESERVE 4 | |
47 | #define IO_DQS_OUT_RESERVE 6 | |
48 | #define IO_DQ_OUT_RESERVE 0 | |
49 | #define IO_IO_IN_DELAY_MAX 31 | |
50 | #define IO_IO_OUT1_DELAY_MAX 31 | |
51 | #define IO_IO_OUT2_DELAY_MAX 0 | |
52 | #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 | |
53 | #define MARGIN_VARIATION_TEST 0 | |
54 | #define MAX_LATENCY_COUNT_WIDTH 5 | |
55 | #define MEM_ADDR_WIDTH 13 | |
56 | #define READ_VALID_FIFO_SIZE 16 | |
3da42859 | 57 | #define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c |
3da42859 DN |
58 | #define RW_MGR_MEM_ADDRESS_MIRRORING 0 |
59 | #define RW_MGR_MEM_ADDRESS_WIDTH 15 | |
60 | #define RW_MGR_MEM_BANK_WIDTH 3 | |
61 | #define RW_MGR_MEM_CHIP_SELECT_WIDTH 1 | |
62 | #define RW_MGR_MEM_CLK_EN_WIDTH 1 | |
63 | #define RW_MGR_MEM_CONTROL_WIDTH 1 | |
64 | #define RW_MGR_MEM_DATA_MASK_WIDTH 5 | |
65 | #define RW_MGR_MEM_DATA_WIDTH 40 | |
66 | #define RW_MGR_MEM_DQ_PER_READ_DQS 8 | |
67 | #define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 | |
68 | #define RW_MGR_MEM_IF_READ_DQS_WIDTH 5 | |
69 | #define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5 | |
70 | #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 | |
cf96848b | 71 | #define RW_MGR_MEM_NUMBER_OF_RANKS 1 |
3da42859 DN |
72 | #define RW_MGR_MEM_ODT_WIDTH 1 |
73 | #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 | |
74 | #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 | |
75 | #define RW_MGR_MR0_BL 1 | |
76 | #define RW_MGR_MR0_CAS_LATENCY 3 | |
77 | #define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5 | |
78 | #define RW_MGR_WRITE_TO_DEBUG_READ 1.0 | |
79 | #define SKEW_CALIBRATION 0 | |
80 | #define TINIT_CNTR1_VAL 32 | |
81 | #define TINIT_CNTR2_VAL 32 | |
82 | #define TINIT_CNTR0_VAL 132 | |
83 | #define TRESET_CNTR1_VAL 99 | |
84 | #define TRESET_CNTR2_VAL 10 | |
85 | #define TRESET_CNTR0_VAL 132 | |
86 | ||
87 | #endif /* _SEQUENCER_DEFINES_H_ */ |