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16c0cc1c SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/processor.h> | |
26 | ||
27 | extern void board_pll_init_f(void); | |
28 | ||
e673226f | 29 | static void acadia_gpio_init(void) |
16c0cc1c SR |
30 | { |
31 | /* | |
32 | * GPIO0 setup (select GPIO or alternate function) | |
33 | */ | |
6d0f6bcf JCPV |
34 | out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); |
35 | out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ | |
36 | out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); | |
37 | out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ | |
38 | out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); | |
39 | out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ | |
40 | out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ | |
16c0cc1c SR |
41 | |
42 | /* | |
43 | * Ultra (405EZ) was nice enough to add another GPIO controller | |
44 | */ | |
6d0f6bcf JCPV |
45 | out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */ |
46 | out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL); | |
47 | out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */ | |
48 | out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L); | |
49 | out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */ | |
50 | out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL); | |
51 | out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */ | |
16c0cc1c SR |
52 | } |
53 | ||
16c0cc1c SR |
54 | int board_early_init_f(void) |
55 | { | |
56 | unsigned int reg; | |
57 | ||
df8a24cd | 58 | #if !defined(CONFIG_NAND_U_BOOT) |
e673226f | 59 | /* don't reinit PLL when booting via I2C bootstrap option */ |
d1c3b275 | 60 | mfsdr(SDR0_PINSTP, reg); |
e673226f SR |
61 | if (reg != 0xf0000000) |
62 | board_pll_init_f(); | |
df8a24cd | 63 | #endif |
e673226f SR |
64 | |
65 | acadia_gpio_init(); | |
16c0cc1c | 66 | |
5d4a1790 | 67 | /* Configure 405EZ for NAND usage */ |
d1c3b275 SR |
68 | mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); |
69 | mfsdr(SDR0_ULTRA0, reg); | |
c440bfe6 | 70 | reg &= ~SDR_ULTRA0_CSN_MASK; |
6d0f6bcf | 71 | reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) | |
c440bfe6 SR |
72 | SDR_ULTRA0_NDGPIOBP | |
73 | SDR_ULTRA0_EBCRDYEN | | |
74 | SDR_ULTRA0_NFSRSTEN; | |
d1c3b275 | 75 | mtsdr(SDR0_ULTRA0, reg); |
5d4a1790 | 76 | |
16c0cc1c | 77 | /* USB Host core needs this bit set */ |
d1c3b275 SR |
78 | mfsdr(SDR0_ULTRA1, reg); |
79 | mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE); | |
16c0cc1c | 80 | |
952e7760 SR |
81 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
82 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ | |
83 | mtdcr(UIC0CR, 0x00000010); | |
84 | mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */ | |
85 | mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ | |
86 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
16c0cc1c SR |
87 | |
88 | return 0; | |
89 | } | |
90 | ||
91 | int misc_init_f(void) | |
92 | { | |
93 | /* Set EPLD to take PHY out of reset */ | |
6d0f6bcf | 94 | out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00); |
16c0cc1c SR |
95 | udelay(100000); |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | /* | |
101 | * Check Board Identity: | |
102 | */ | |
103 | int checkboard(void) | |
104 | { | |
105 | char *s = getenv("serial#"); | |
5d4a1790 SR |
106 | u8 rev; |
107 | ||
6d0f6bcf | 108 | rev = in8(CONFIG_SYS_CPLD_BASE + 0); |
5d4a1790 | 109 | printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev); |
16c0cc1c | 110 | |
16c0cc1c SR |
111 | if (s != NULL) { |
112 | puts(", serial# "); | |
113 | puts(s); | |
114 | } | |
115 | putc('\n'); | |
116 | ||
117 | return (0); | |
118 | } |