]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/amcc/acadia/acadia.c
drivers, block: remove sil680 driver
[people/ms/u-boot.git] / board / amcc / acadia / acadia.c
CommitLineData
16c0cc1c
SR
1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
16c0cc1c
SR
6 */
7
8#include <common.h>
9#include <asm/processor.h>
10
11extern void board_pll_init_f(void);
12
e673226f 13static void acadia_gpio_init(void)
16c0cc1c
SR
14{
15 /*
16 * GPIO0 setup (select GPIO or alternate function)
17 */
6d0f6bcf
JCPV
18 out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
19 out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
20 out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
21 out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
22 out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
23 out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
24 out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
16c0cc1c
SR
25
26 /*
27 * Ultra (405EZ) was nice enough to add another GPIO controller
28 */
6d0f6bcf
JCPV
29 out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */
30 out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
31 out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */
32 out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
33 out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */
34 out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
35 out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */
16c0cc1c
SR
36}
37
16c0cc1c
SR
38int board_early_init_f(void)
39{
40 unsigned int reg;
41
e673226f 42 /* don't reinit PLL when booting via I2C bootstrap option */
d1c3b275 43 mfsdr(SDR0_PINSTP, reg);
e673226f
SR
44 if (reg != 0xf0000000)
45 board_pll_init_f();
46
47 acadia_gpio_init();
16c0cc1c 48
5d4a1790 49 /* Configure 405EZ for NAND usage */
d1c3b275
SR
50 mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
51 mfsdr(SDR0_ULTRA0, reg);
c440bfe6 52 reg &= ~SDR_ULTRA0_CSN_MASK;
6d0f6bcf 53 reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
c440bfe6
SR
54 SDR_ULTRA0_NDGPIOBP |
55 SDR_ULTRA0_EBCRDYEN |
56 SDR_ULTRA0_NFSRSTEN;
d1c3b275 57 mtsdr(SDR0_ULTRA0, reg);
5d4a1790 58
16c0cc1c 59 /* USB Host core needs this bit set */
d1c3b275
SR
60 mfsdr(SDR0_ULTRA1, reg);
61 mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
16c0cc1c 62
952e7760
SR
63 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
64 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
65 mtdcr(UIC0CR, 0x00000010);
66 mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */
67 mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
68 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
16c0cc1c
SR
69
70 return 0;
71}
72
73int misc_init_f(void)
74{
75 /* Set EPLD to take PHY out of reset */
6d0f6bcf 76 out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
16c0cc1c
SR
77 udelay(100000);
78
79 return 0;
80}
81
82/*
83 * Check Board Identity:
84 */
85int checkboard(void)
86{
f0c0b3a9
WD
87 char buf[64];
88 int i = getenv_f("serial#", buf, sizeof(buf));
5d4a1790
SR
89 u8 rev;
90
6d0f6bcf 91 rev = in8(CONFIG_SYS_CPLD_BASE + 0);
5d4a1790 92 printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
16c0cc1c 93
f0c0b3a9 94 if (i > 0) {
16c0cc1c 95 puts(", serial# ");
f0c0b3a9 96 puts(buf);
16c0cc1c
SR
97 }
98 putc('\n');
99
100 return (0);
101}