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drivers, block: remove sil680 driver
[people/ms/u-boot.git] / board / amcc / acadia / memory.c
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1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
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8/* define DEBUG for debugging output (obviously ;-)) */
9#if 0
10#define DEBUG
11#endif
12
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13#include <common.h>
14#include <asm/processor.h>
3cb86f3e 15#include <asm/io.h>
09887762 16#include <asm/ppc4xx-gpio.h>
16c0cc1c 17
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18DECLARE_GLOBAL_DATA_PTR;
19
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20extern void board_pll_init_f(void);
21
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22static void cram_bcr_write(u32 wr_val)
23{
3cb86f3e 24 wr_val <<= 2;
16c0cc1c 25
3cb86f3e 26 /* set CRAM_CRE to 1 */
6d0f6bcf 27 gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
16c0cc1c 28
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29 /* Write BCR to CRAM on CS1 */
30 out32(wr_val + 0x00200000, 0);
31 debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
16c0cc1c 32
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33 /* Write BCR to CRAM on CS2 */
34 out32(wr_val + 0x02200000, 0);
35 debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
16c0cc1c 36
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37 sync();
38 eieio();
16c0cc1c 39
3cb86f3e 40 /* set CRAM_CRE back to 0 (normal operation) */
6d0f6bcf 41 gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
16c0cc1c 42
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43 return;
44}
45
f1683aa7 46int dram_init(void)
16c0cc1c 47{
c440bfe6 48 int i;
3cb86f3e 49 u32 val;
16c0cc1c 50
3cb86f3e 51 /* 1. EBC need to program READY, CLK, ADV for ASync mode */
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JCPV
52 gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
53 gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
54 gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
55 gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
16c0cc1c 56
3cb86f3e 57 /* 2. EBC in Async mode */
d1c3b275
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58 mtebc(PB1AP, 0x078F1EC0);
59 mtebc(PB2AP, 0x078F1EC0);
60 mtebc(PB1CR, 0x000BC000);
61 mtebc(PB2CR, 0x020BC000);
16c0cc1c 62
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63 /* 3. Set CRAM in Sync mode */
64 cram_bcr_write(0x7012); /* CRAM burst setting */
16c0cc1c 65
3cb86f3e 66 /* 4. EBC in Sync mode */
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67 mtebc(PB1AP, 0x9C0201C0);
68 mtebc(PB2AP, 0x9C0201C0);
16c0cc1c 69
3cb86f3e 70 /* Set GPIO pins back to alternate function */
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JCPV
71 gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
72 gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
16c0cc1c 73
3cb86f3e 74 /* Config EBC to use RDY */
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75 mfsdr(SDR0_ULTRA0, val);
76 mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
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77
78 /* Wait a short while, since for NAND booting this is too fast */
79 for (i=0; i<200000; i++)
80 ;
16c0cc1c 81
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82 gd->ram_size = CONFIG_SYS_MBYTES_RAM << 20;
83
84 return 0;
16c0cc1c 85}