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Commit | Line | Data |
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16c0cc1c SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
16c0cc1c SR |
6 | */ |
7 | ||
3cb86f3e SR |
8 | /* define DEBUG for debugging output (obviously ;-)) */ |
9 | #if 0 | |
10 | #define DEBUG | |
11 | #endif | |
12 | ||
16c0cc1c SR |
13 | #include <common.h> |
14 | #include <asm/processor.h> | |
3cb86f3e | 15 | #include <asm/io.h> |
09887762 | 16 | #include <asm/ppc4xx-gpio.h> |
16c0cc1c | 17 | |
088454cd SG |
18 | DECLARE_GLOBAL_DATA_PTR; |
19 | ||
df8a24cd SR |
20 | extern void board_pll_init_f(void); |
21 | ||
16c0cc1c SR |
22 | static void cram_bcr_write(u32 wr_val) |
23 | { | |
3cb86f3e | 24 | wr_val <<= 2; |
16c0cc1c | 25 | |
3cb86f3e | 26 | /* set CRAM_CRE to 1 */ |
6d0f6bcf | 27 | gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1); |
16c0cc1c | 28 | |
3cb86f3e SR |
29 | /* Write BCR to CRAM on CS1 */ |
30 | out32(wr_val + 0x00200000, 0); | |
31 | debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000); | |
16c0cc1c | 32 | |
3cb86f3e SR |
33 | /* Write BCR to CRAM on CS2 */ |
34 | out32(wr_val + 0x02200000, 0); | |
35 | debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000); | |
16c0cc1c | 36 | |
3cb86f3e SR |
37 | sync(); |
38 | eieio(); | |
16c0cc1c | 39 | |
3cb86f3e | 40 | /* set CRAM_CRE back to 0 (normal operation) */ |
6d0f6bcf | 41 | gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0); |
16c0cc1c | 42 | |
16c0cc1c SR |
43 | return; |
44 | } | |
45 | ||
f1683aa7 | 46 | int dram_init(void) |
16c0cc1c | 47 | { |
c440bfe6 | 48 | int i; |
3cb86f3e | 49 | u32 val; |
16c0cc1c | 50 | |
3cb86f3e | 51 | /* 1. EBC need to program READY, CLK, ADV for ASync mode */ |
6d0f6bcf JCPV |
52 | gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); |
53 | gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); | |
54 | gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); | |
55 | gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); | |
16c0cc1c | 56 | |
3cb86f3e | 57 | /* 2. EBC in Async mode */ |
d1c3b275 SR |
58 | mtebc(PB1AP, 0x078F1EC0); |
59 | mtebc(PB2AP, 0x078F1EC0); | |
60 | mtebc(PB1CR, 0x000BC000); | |
61 | mtebc(PB2CR, 0x020BC000); | |
16c0cc1c | 62 | |
3cb86f3e SR |
63 | /* 3. Set CRAM in Sync mode */ |
64 | cram_bcr_write(0x7012); /* CRAM burst setting */ | |
16c0cc1c | 65 | |
3cb86f3e | 66 | /* 4. EBC in Sync mode */ |
d1c3b275 SR |
67 | mtebc(PB1AP, 0x9C0201C0); |
68 | mtebc(PB2AP, 0x9C0201C0); | |
16c0cc1c | 69 | |
3cb86f3e | 70 | /* Set GPIO pins back to alternate function */ |
6d0f6bcf JCPV |
71 | gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); |
72 | gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); | |
16c0cc1c | 73 | |
3cb86f3e | 74 | /* Config EBC to use RDY */ |
d1c3b275 SR |
75 | mfsdr(SDR0_ULTRA0, val); |
76 | mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN); | |
c440bfe6 SR |
77 | |
78 | /* Wait a short while, since for NAND booting this is too fast */ | |
79 | for (i=0; i<200000; i++) | |
80 | ; | |
16c0cc1c | 81 | |
088454cd SG |
82 | gd->ram_size = CONFIG_SYS_MBYTES_RAM << 20; |
83 | ||
84 | return 0; | |
16c0cc1c | 85 | } |