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[people/ms/u-boot.git] / board / amcc / bamboo / bamboo.c
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8a316c9b 1/*
a471db07 2 * (C) Copyright 2005-2007
8a316c9b
SR		 3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
8a316c9b
SR		 6 */
7
8#include <common.h>
9#include <asm/processor.h>
09887762 10#include <asm/ppc4xx-gpio.h>
8a316c9b 11#include <spd_sdram.h>
b36df561 12#include <asm/ppc440.h>
17f50f22 13#include "bamboo.h"
8a316c9b 14
17f50f22
SR		 15void ext_bus_cntlr_init(void);
16void configure_ppc440ep_pins(void);
c57c7980 17int is_nand_selected(void);
8a316c9b 18
d2f68006
EO		 19#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
20/*************************************************************************
21 *
22 * Bamboo has one bank onboard sdram (plus DIMM)
23 *
24 * Fixed memory is composed of :
25 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
26 * 13 row add bits, 10 column add bits (but 12 row used only).
27 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
28 * 12 row add bits, 10 column add bits.
29 * Prepare a subset (only the used ones) of SPD data
30 *
31 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
32 * the corresponding bank is divided by 2 due to number of Row addresses
33 * 12 in the ECC module
34 *
35 * Assumes: 64 MB, ECC, non-registered
36 * PLB @ 133 MHz
37 *
38 ************************************************************************/
39const unsigned char cfg_simulate_spd_eeprom[128] = {
40 0x80, /* number of SPD bytes used: 128 */
41 0x08, /* total number bytes in SPD device = 256 */
42 0x07, /* DDR ram */
43#ifdef CONFIG_DDR_ECC
44 0x0C, /* num Row Addr: 12 */
45#else
46 0x0D, /* num Row Addr: 13 */
47#endif
48 0x09, /* numColAddr: 9 */
49 0x01, /* numBanks: 1 */
50 0x20, /* Module data width: 32 bits */
51 0x00, /* Module data width continued: +0 */
52 0x04, /* 2.5 Volt */
53 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
9f798766 54 0x00, /* SDRAM Access from clock */
d2f68006
EO		 55#ifdef CONFIG_DDR_ECC
56 0x02, /* ECC ON : 02 OFF : 00 */
57#else
58 0x00, /* ECC ON : 02 OFF : 00 */
59#endif
9f798766 60 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
d2f68006
EO		 61 0,
62 0,
63 0x01, /* wcsbc = 1 */
64 0,
65 0,
66 0x0C, /* casBit (2,2.5) */
67 0,
68 0,
69 0x00, /* not registered: 0 registered : 0x02*/
70 0,
71 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
72 0,
73 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
74 0,
75 0x50, /* tRpNs = 20 ns */
76 0,
77 0x50, /* tRcdNs = 20 ns */
78 45, /* tRasNs */
79#ifdef CONFIG_DDR_ECC
80 0x08, /* bankSizeID: 32MB */
81#else
82 0x10, /* bankSizeID: 64MB */
83#endif
84 0,
85 0,
86 0,
87 0,
88 0,
89 0,
90 0,
91 0,
92 0,
93 0,
94 0,
95 0,
96 0,
97 0,
98 0,
99 0,
100 0,
101 0,
102 0,
103 0,
104 0,
105 0,
106 0,
107 0,
108 0,
109 0,
110 0,
111 0,
112 0,
113 0,
114 0,
115 0,
116 0,
117 0,
118 0,
119 0,
120 0,
121 0,
122 0,
123 0,
124 0,
125 0,
126 0,
127 0,
128 0,
129 0,
130 0,
131 0,
132 0,
133 0,
134 0,
135 0,
136 0,
137 0,
138 0,
139 0,
140 0,
141 0,
142 0,
143 0,
144 0,
145 0,
146 0,
147 0,
148 0,
149 0,
150 0,
151 0,
152 0,
153 0,
154 0,
155 0,
156 0,
157 0,
158 0,
159 0,
160 0,
161 0,
162 0,
163 0,
164 0,
165 0,
166 0,
167 0,
168 0,
169 0,
170 0,
171 0,
172 0,
173 0,
174 0,
175 0,
176 0,
177 0,
178 0,
179 0
180};
181#endif
fd49bf02 182
17f50f22 183#if 0
f901a83b
WD		 184{ /* GPIO Alternate1 Alternate2 Alternate3 */
185 {
186 /* GPIO Core 0 */
187 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
188 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
189 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
190 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
191 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
192 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
193 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
194 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
195 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
196 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
197 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
198 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
199 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
200 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
201 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
202 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
203 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
204 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
205 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
206 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
207 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
208 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
209 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
210 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
211 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
212 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
213 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
214 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
215 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
216 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
217 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
218 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
219 },
220 {
221 /* GPIO Core 1 */
222 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
223 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
224 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
225 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
226 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
227 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
228 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
229 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
230 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
231 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
232 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
233 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
234 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
235 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
236 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
237 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
238 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
239 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
240 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
241 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
242 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
243 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
244 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
245 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
246 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
247 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
248 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
249 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
250 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
251 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
252 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
253 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
254 }
17f50f22
SR		 255};
256#endif
8a316c9b 257
17f50f22
SR		 258/*----------------------------------------------------------------------------+
259 | EBC Devices Characteristics
f901a83b
WD		 260 | Peripheral Bank Access Parameters - EBC0_BnAP
261 | Peripheral Bank Configuration Register - EBC0_BnCR
17f50f22
SR		 262 +----------------------------------------------------------------------------*/
263/* Small Flash */
f901a83b
WD		 264#define EBC0_BNAP_SMALL_FLASH \
265 EBC0_BNAP_BME_DISABLED | \
266 EBC0_BNAP_TWT_ENCODE(6) | \
53677ef1
WD		 267 EBC0_BNAP_CSN_ENCODE(0) | \
268 EBC0_BNAP_OEN_ENCODE(1) | \
269 EBC0_BNAP_WBN_ENCODE(1) | \
270 EBC0_BNAP_WBF_ENCODE(3) | \
271 EBC0_BNAP_TH_ENCODE(1) | \
272 EBC0_BNAP_RE_ENABLED | \
273 EBC0_BNAP_SOR_DELAYED | \
274 EBC0_BNAP_BEM_WRITEONLY | \
17f50f22 275 EBC0_BNAP_PEN_DISABLED
8a316c9b 276
f901a83b 277#define EBC0_BNCR_SMALL_FLASH_CS0 \
53677ef1
WD		 278 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
279 EBC0_BNCR_BS_1MB | \
280 EBC0_BNCR_BU_RW | \
17f50f22 281 EBC0_BNCR_BW_8BIT
8a316c9b 282
f901a83b 283#define EBC0_BNCR_SMALL_FLASH_CS4 \
53677ef1
WD		 284 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
285 EBC0_BNCR_BS_1MB | \
286 EBC0_BNCR_BU_RW | \
c57c7980 287 EBC0_BNCR_BW_8BIT
17f50f22
SR		 288
289/* Large Flash or SRAM */
f901a83b 290#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
53677ef1
WD		 291 EBC0_BNAP_BME_DISABLED | \
292 EBC0_BNAP_TWT_ENCODE(8) | \
293 EBC0_BNAP_CSN_ENCODE(0) | \
294 EBC0_BNAP_OEN_ENCODE(1) | \
295 EBC0_BNAP_WBN_ENCODE(1) | \
296 EBC0_BNAP_WBF_ENCODE(1) | \
297 EBC0_BNAP_TH_ENCODE(2) | \
298 EBC0_BNAP_SOR_DELAYED | \
299 EBC0_BNAP_BEM_RW | \
17f50f22
SR		 300 EBC0_BNAP_PEN_DISABLED
301
53677ef1
WD		 302#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
303 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
304 EBC0_BNCR_BS_8MB | \
305 EBC0_BNCR_BU_RW | \
17f50f22
SR		 306 EBC0_BNCR_BW_16BIT
307
308
53677ef1
WD		 309#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
310 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
311 EBC0_BNCR_BS_8MB | \
312 EBC0_BNCR_BU_RW | \
17f50f22 313 EBC0_BNCR_BW_16BIT
8a316c9b 314
17f50f22 315/* NVRAM - FPGA */
f901a83b 316#define EBC0_BNAP_NVRAM_FPGA \
53677ef1
WD		 317 EBC0_BNAP_BME_DISABLED | \
318 EBC0_BNAP_TWT_ENCODE(9) | \
319 EBC0_BNAP_CSN_ENCODE(0) | \
320 EBC0_BNAP_OEN_ENCODE(1) | \
321 EBC0_BNAP_WBN_ENCODE(1) | \
322 EBC0_BNAP_WBF_ENCODE(0) | \
323 EBC0_BNAP_TH_ENCODE(2) | \
324 EBC0_BNAP_RE_ENABLED | \
325 EBC0_BNAP_SOR_DELAYED | \
326 EBC0_BNAP_BEM_WRITEONLY | \
17f50f22 327 EBC0_BNAP_PEN_DISABLED
8a316c9b 328
f901a83b 329#define EBC0_BNCR_NVRAM_FPGA_CS5 \
53677ef1
WD		 330 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
331 EBC0_BNCR_BS_1MB | \
332 EBC0_BNCR_BU_RW | \
17f50f22 333 EBC0_BNCR_BW_8BIT
8a316c9b 334
17f50f22 335/* Nand Flash */
f901a83b 336#define EBC0_BNAP_NAND_FLASH \
53677ef1
WD		 337 EBC0_BNAP_BME_DISABLED | \
338 EBC0_BNAP_TWT_ENCODE(3) | \
339 EBC0_BNAP_CSN_ENCODE(0) | \
340 EBC0_BNAP_OEN_ENCODE(0) | \
341 EBC0_BNAP_WBN_ENCODE(0) | \
342 EBC0_BNAP_WBF_ENCODE(0) | \
343 EBC0_BNAP_TH_ENCODE(1) | \
344 EBC0_BNAP_RE_ENABLED | \
345 EBC0_BNAP_SOR_NOT_DELAYED | \
346 EBC0_BNAP_BEM_RW | \
17f50f22
SR		 347 EBC0_BNAP_PEN_DISABLED
348
349
f901a83b 350#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
17f50f22
SR		 351
352/* NAND0 */
f901a83b 353#define EBC0_BNCR_NAND_FLASH_CS1 \
53677ef1
WD		 354 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
355 EBC0_BNCR_BS_1MB | \
356 EBC0_BNCR_BU_RW | \
17f50f22
SR		 357 EBC0_BNCR_BW_32BIT
358/* NAND1 - Bank2 */
f901a83b 359#define EBC0_BNCR_NAND_FLASH_CS2 \
53677ef1
WD		 360 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
361 EBC0_BNCR_BS_1MB | \
362 EBC0_BNCR_BU_RW | \
17f50f22
SR		 363 EBC0_BNCR_BW_32BIT
364
365/* NAND1 - Bank3 */
f901a83b 366#define EBC0_BNCR_NAND_FLASH_CS3 \
53677ef1
WD		 367 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
368 EBC0_BNCR_BS_1MB | \
369 EBC0_BNCR_BU_RW | \
17f50f22
SR		 370 EBC0_BNCR_BW_32BIT
371
372int board_early_init_f(void)
373{
374 ext_bus_cntlr_init();
8a316c9b
SR		 375
376 /*--------------------------------------------------------------------
377 * Setup the interrupt controller polarities, triggers, etc.
378 *-------------------------------------------------------------------*/
952e7760
SR		 379 mtdcr(UIC0SR, 0xffffffff); /* clear all */
380 mtdcr(UIC0ER, 0x00000000); /* disable all */
381 mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
382 mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
383 mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
384 mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
385 mtdcr(UIC0SR, 0xffffffff); /* clear all */
8a316c9b 386
952e7760
SR		 387 mtdcr(UIC1SR, 0xffffffff); /* clear all */
388 mtdcr(UIC1ER, 0x00000000); /* disable all */
389 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
390 mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
391 mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
392 mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
393 mtdcr(UIC1SR, 0xffffffff); /* clear all */
8a316c9b
SR		 394
395 /*--------------------------------------------------------------------
396 * Setup the GPIO pins
397 *-------------------------------------------------------------------*/
17f50f22
SR		 398 out32(GPIO0_OSRL, 0x00000400);
399 out32(GPIO0_OSRH, 0x00000000);
400 out32(GPIO0_TSRL, 0x00000400);
401 out32(GPIO0_TSRH, 0x00000000);
402 out32(GPIO0_ISR1L, 0x00000000);
403 out32(GPIO0_ISR1H, 0x00000000);
404 out32(GPIO0_ISR2L, 0x00000000);
405 out32(GPIO0_ISR2H, 0x00000000);
406 out32(GPIO0_ISR3L, 0x00000000);
407 out32(GPIO0_ISR3H, 0x00000000);
8a316c9b 408
17f50f22
SR		 409 out32(GPIO1_OSRL, 0x0C380000);
410 out32(GPIO1_OSRH, 0x00000000);
411 out32(GPIO1_TSRL, 0x0C380000);
412 out32(GPIO1_TSRH, 0x00000000);
413 out32(GPIO1_ISR1L, 0x0FC30000);
414 out32(GPIO1_ISR1H, 0x00000000);
415 out32(GPIO1_ISR2L, 0x0C010000);
416 out32(GPIO1_ISR2H, 0x00000000);
417 out32(GPIO1_ISR3L, 0x01400000);
418 out32(GPIO1_ISR3H, 0x00000000);
8a316c9b 419
17f50f22 420 configure_ppc440ep_pins();
8a316c9b
SR		 421
422 return 0;
423}
424
425int checkboard(void)
426{
f0c0b3a9
WD		 427 char buf[64];
428 int i = getenv_f("serial#", buf, sizeof(buf));
8a316c9b
SR		 429
430 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
f0c0b3a9 431 if (i > 0) {
8a316c9b 432 puts(", serial# ");
f0c0b3a9 433 puts(buf);
8a316c9b
SR		 434 }
435 putc('\n');
436
8a316c9b
SR		 437 return (0);
438}
439
8a316c9b 440
9973e3c6 441phys_size_t initdram (int board_type)
8a316c9b 442{
a471db07
SR		 443#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
444 long dram_size;
17f50f22 445
d19206b9 446 dram_size = spd_sdram();
17f50f22
SR		 447
448 return dram_size;
a471db07 449#else
6d0f6bcf 450 return CONFIG_SYS_MBYTES_SDRAM << 20;
a471db07 451#endif
8a316c9b
SR		 452}
453
17f50f22
SR		 454/*----------------------------------------------------------------------------+
455 | is_powerpc440ep_pass1.
456 +----------------------------------------------------------------------------*/
457int is_powerpc440ep_pass1(void)
458{
459 unsigned long pvr;
460
461 pvr = get_pvr();
462
463 if (pvr == PVR_POWERPC_440EP_PASS1)
472d5460 464 return true;
17f50f22 465 else if (pvr == PVR_POWERPC_440EP_PASS2)
472d5460 466 return false;
17f50f22
SR		 467 else {
468 printf("brdutil error 3\n");
469 for (;;)
470 ;
471 }
472
472d5460 473 return false;
17f50f22
SR		 474}
475
476/*----------------------------------------------------------------------------+
477 | is_nand_selected.
478 +----------------------------------------------------------------------------*/
479int is_nand_selected(void)
480{
c57c7980 481#ifdef CONFIG_BAMBOO_NAND
472d5460 482 return true;
c57c7980 483#else
472d5460 484 return false;
c57c7980 485#endif
17f50f22
SR		 486}
487
488/*----------------------------------------------------------------------------+
489 | config_on_ebc_cs4_is_small_flash => from EPLD
490 +----------------------------------------------------------------------------*/
491unsigned char config_on_ebc_cs4_is_small_flash(void)
492{
493 /* Not implemented yet => returns constant value */
472d5460 494 return true;
17f50f22
SR		 495}
496
497/*----------------------------------------------------------------------------+
498 | Ext_bus_cntlr_init.
499 | Initialize the external bus controller
500 +----------------------------------------------------------------------------*/
501void ext_bus_cntlr_init(void)
502{
503 unsigned long sdr0_pstrp0, sdr0_sdstp1;
504 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
f901a83b 505 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
17f50f22
SR		 506 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
507 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
508 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
509 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
510 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
511
512
513 /*-------------------------------------------------------------------------+
514 |
515 | PART 1 : Initialize EBC Bank 5
516 | ==============================
517 | Bank5 is always associated to the NVRAM/EPLD.
518 | It has to be initialized prior to other banks settings computation since
519 | some board registers values may be needed
520 |
521 +-------------------------------------------------------------------------*/
522 /* NVRAM - FPGA */
d1c3b275
SR		 523 mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
524 mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
17f50f22
SR		 525
526 /*-------------------------------------------------------------------------+
527 |
528 | PART 2 : Determine which boot device was selected
529 | =========================================
530 |
531 | Read Pin Strap Register in PPC440EP
532 | In case of boot from IIC, read Serial Device Strap Register1
533 |
534 | Result can either be :
535 | - Boot from EBC 8bits => SMALL FLASH
536 | - Boot from EBC 16bits => Large Flash or SRAM
537 | - Boot from NAND Flash
538 | - Boot from PCI
539 |
540 +-------------------------------------------------------------------------*/
541 /* Read Pin Strap Register in PPC440EP */
5e7abce9 542 mfsdr(SDR0_PINSTP, sdr0_pstrp0);
17f50f22
SR		 543 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
544
545 /*-------------------------------------------------------------------------+
546 | PPC440EP Pass1
547 +-------------------------------------------------------------------------*/
472d5460 548 if (is_powerpc440ep_pass1() == true) {
17f50f22
SR		 549 switch(bootstrap_settings) {
550 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
551 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
552 /* Boot from Small Flash */
553 computed_boot_device = BOOT_FROM_SMALL_FLASH;
554 break;
555 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
556 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
557 /* Boot from PCI */
558 computed_boot_device = BOOT_FROM_PCI;
559 break;
560
561 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
562 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
563 /* Boot from Nand Flash */
564 computed_boot_device = BOOT_FROM_NAND_FLASH0;
565 break;
566
567 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
568 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
569 /* Boot from Small Flash */
570 computed_boot_device = BOOT_FROM_SMALL_FLASH;
571 break;
572
573 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
574 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
575 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
576 /* Read Serial Device Strap Register1 in PPC440EP */
d1c3b275 577 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
f901a83b
WD		 578 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
579 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
17f50f22
SR		 580
581 switch(boot_selection) {
582 case SDR0_SDSTP1_BOOT_SEL_EBC:
583 switch(ebc_boot_size) {
584 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
585 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
586 break;
587 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
588 computed_boot_device = BOOT_FROM_SMALL_FLASH;
589 break;
590 }
591 break;
592
593 case SDR0_SDSTP1_BOOT_SEL_PCI:
594 computed_boot_device = BOOT_FROM_PCI;
595 break;
596
597 case SDR0_SDSTP1_BOOT_SEL_NDFC:
598 computed_boot_device = BOOT_FROM_NAND_FLASH0;
599 break;
600 }
601 break;
602 }
603 }
604
605 /*-------------------------------------------------------------------------+
606 | PPC440EP Pass2
607 +-------------------------------------------------------------------------*/
608 else {
609 switch(bootstrap_settings) {
610 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
611 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
612 /* Boot from Small Flash */
613 computed_boot_device = BOOT_FROM_SMALL_FLASH;
614 break;
615 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
616 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
617 /* Boot from PCI */
618 computed_boot_device = BOOT_FROM_PCI;
619 break;
620
621 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
622 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
623 /* Boot from Nand Flash */
624 computed_boot_device = BOOT_FROM_NAND_FLASH0;
625 break;
626
627 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
628 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
629 /* Boot from Large Flash or SRAM */
630 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
631 break;
632
633 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
634 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
635 /* Boot from Large Flash or SRAM */
636 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
637 break;
638
639 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
640 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
641 /* Boot from PCI */
642 computed_boot_device = BOOT_FROM_PCI;
643 break;
644
645 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
646 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
647 /* Default Strap Settings 5-7 */
648 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
649 /* Read Serial Device Strap Register1 in PPC440EP */
d1c3b275 650 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
f901a83b
WD		 651 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
652 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
17f50f22
SR		 653
654 switch(boot_selection) {
655 case SDR0_SDSTP1_BOOT_SEL_EBC:
656 switch(ebc_boot_size) {
657 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
658 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
659 break;
660 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
661 computed_boot_device = BOOT_FROM_SMALL_FLASH;
662 break;
663 }
664 break;
665
666 case SDR0_SDSTP1_BOOT_SEL_PCI:
667 computed_boot_device = BOOT_FROM_PCI;
668 break;
669
670 case SDR0_SDSTP1_BOOT_SEL_NDFC:
671 computed_boot_device = BOOT_FROM_NAND_FLASH0;
672 break;
673 }
674 break;
675 }
676 }
677
678 /*-------------------------------------------------------------------------+
679 |
680 | PART 3 : Compute EBC settings depending on selected boot device
681 | ====== ======================================================
682 |
683 | Resulting EBC init will be among following configurations :
684 |
685 | - Boot from EBC 8bits => boot from SMALL FLASH selected
f901a83b
WD		 686 | EBC-CS0 = Small Flash
687 | EBC-CS1,2,3 = NAND Flash or
688 | Exp.Slot depending on Soft Config
689 | EBC-CS4 = SRAM/Large Flash or
690 | Large Flash/SRAM depending on jumpers
691 | EBC-CS5 = NVRAM / EPLD
17f50f22
SR		 692 |
693 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
f901a83b
WD		 694 | EBC-CS0 = SRAM/Large Flash or
695 | Large Flash/SRAM depending on jumpers
696 | EBC-CS1,2,3 = NAND Flash or
697 | Exp.Slot depending on Software Configuration
698 | EBC-CS4 = Small Flash
699 | EBC-CS5 = NVRAM / EPLD
17f50f22
SR		 700 |
701 | - Boot from NAND Flash
f901a83b
WD		 702 | EBC-CS0 = NAND Flash0
703 | EBC-CS1,2,3 = NAND Flash1
704 | EBC-CS4 = SRAM/Large Flash or
705 | Large Flash/SRAM depending on jumpers
706 | EBC-CS5 = NVRAM / EPLD
17f50f22
SR		 707 |
708 | - Boot from PCI
f901a83b
WD		 709 | EBC-CS0 = ...
710 | EBC-CS1,2,3 = NAND Flash or
711 | Exp.Slot depending on Software Configuration
712 | EBC-CS4 = SRAM/Large Flash or
713 | Large Flash/SRAM or
714 | Small Flash depending on jumpers
715 | EBC-CS5 = NVRAM / EPLD
17f50f22
SR		 716 |
717 +-------------------------------------------------------------------------*/
718
719 switch(computed_boot_device) {
720 /*------------------------------------------------------------------------- */
f901a83b 721 case BOOT_FROM_SMALL_FLASH:
17f50f22
SR		 722 /*------------------------------------------------------------------------- */
723 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
724 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
472d5460 725 if ((is_nand_selected()) == true) {
17f50f22
SR		 726 /* NAND Flash */
727 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
728 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
c57c7980
SR		 729 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
730 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
17f50f22
SR		 731 ebc0_cs3_bnap_value = 0;
732 ebc0_cs3_bncr_value = 0;
733 } else {
734 /* Expansion Slot */
735 ebc0_cs1_bnap_value = 0;
736 ebc0_cs1_bncr_value = 0;
737 ebc0_cs2_bnap_value = 0;
738 ebc0_cs2_bncr_value = 0;
739 ebc0_cs3_bnap_value = 0;
740 ebc0_cs3_bncr_value = 0;
741 }
742 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
743 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
744
745 break;
746
747 /*------------------------------------------------------------------------- */
f901a83b 748 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
17f50f22
SR		 749 /*------------------------------------------------------------------------- */
750 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
751 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
472d5460 752 if ((is_nand_selected()) == true) {
17f50f22
SR		 753 /* NAND Flash */
754 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
755 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
756 ebc0_cs2_bnap_value = 0;
757 ebc0_cs2_bncr_value = 0;
758 ebc0_cs3_bnap_value = 0;
759 ebc0_cs3_bncr_value = 0;
760 } else {
761 /* Expansion Slot */
762 ebc0_cs1_bnap_value = 0;
763 ebc0_cs1_bncr_value = 0;
764 ebc0_cs2_bnap_value = 0;
765 ebc0_cs2_bncr_value = 0;
766 ebc0_cs3_bnap_value = 0;
767 ebc0_cs3_bncr_value = 0;
768 }
769 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
770 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
771
772 break;
773
774 /*------------------------------------------------------------------------- */
f901a83b 775 case BOOT_FROM_NAND_FLASH0:
17f50f22 776 /*------------------------------------------------------------------------- */
a471db07
SR		 777 ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
778 ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
17f50f22 779
a471db07
SR		 780 ebc0_cs1_bnap_value = 0;
781 ebc0_cs1_bncr_value = 0;
17f50f22
SR		 782 ebc0_cs2_bnap_value = 0;
783 ebc0_cs2_bncr_value = 0;
784 ebc0_cs3_bnap_value = 0;
785 ebc0_cs3_bncr_value = 0;
786
787 /* Large Flash or SRAM */
788 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
789 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
790
791 break;
792
793 /*------------------------------------------------------------------------- */
f901a83b 794 case BOOT_FROM_PCI:
17f50f22
SR		 795 /*------------------------------------------------------------------------- */
796 ebc0_cs0_bnap_value = 0;
797 ebc0_cs0_bncr_value = 0;
798
472d5460 799 if ((is_nand_selected()) == true) {
17f50f22
SR		 800 /* NAND Flash */
801 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
802 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
803 ebc0_cs2_bnap_value = 0;
804 ebc0_cs2_bncr_value = 0;
805 ebc0_cs3_bnap_value = 0;
806 ebc0_cs3_bncr_value = 0;
807 } else {
808 /* Expansion Slot */
809 ebc0_cs1_bnap_value = 0;
810 ebc0_cs1_bncr_value = 0;
811 ebc0_cs2_bnap_value = 0;
812 ebc0_cs2_bncr_value = 0;
813 ebc0_cs3_bnap_value = 0;
814 ebc0_cs3_bncr_value = 0;
815 }
816
472d5460 817 if ((config_on_ebc_cs4_is_small_flash()) == true) {
17f50f22
SR		 818 /* Small Flash */
819 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
820 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
821 } else {
822 /* Large Flash or SRAM */
823 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
824 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
825 }
826
827 break;
828
829 /*------------------------------------------------------------------------- */
f901a83b 830 case BOOT_DEVICE_UNKNOWN:
17f50f22
SR		 831 /*------------------------------------------------------------------------- */
832 /* Error */
833 break;
834
835 }
836
837
838 /*-------------------------------------------------------------------------+
839 | Initialize EBC CONFIG
840 +-------------------------------------------------------------------------*/
d1c3b275
SR		 841 mtdcr(EBC0_CFGADDR, EBC0_CFG);
842 mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
f901a83b
WD		 843 EBC0_CFG_PTD_ENABLED |
844 EBC0_CFG_RTC_2048PERCLK |
845 EBC0_CFG_EMPL_LOW |
846 EBC0_CFG_EMPH_LOW |
847 EBC0_CFG_CSTC_DRIVEN |
848 EBC0_CFG_BPF_ONEDW |
849 EBC0_CFG_EMS_8BIT |
850 EBC0_CFG_PME_DISABLED |
851 EBC0_CFG_PMT_ENCODE(0) );
17f50f22
SR		 852
853 /*-------------------------------------------------------------------------+
854 | Initialize EBC Bank 0-4
855 +-------------------------------------------------------------------------*/
856 /* EBC Bank0 */
d1c3b275
SR		 857 mtebc(PB0AP, ebc0_cs0_bnap_value);
858 mtebc(PB0CR, ebc0_cs0_bncr_value);
17f50f22 859 /* EBC Bank1 */
d1c3b275
SR		 860 mtebc(PB1AP, ebc0_cs1_bnap_value);
861 mtebc(PB1CR, ebc0_cs1_bncr_value);
17f50f22 862 /* EBC Bank2 */
d1c3b275
SR		 863 mtebc(PB2AP, ebc0_cs2_bnap_value);
864 mtebc(PB2CR, ebc0_cs2_bncr_value);
17f50f22 865 /* EBC Bank3 */
d1c3b275
SR		 866 mtebc(PB3AP, ebc0_cs3_bnap_value);
867 mtebc(PB3CR, ebc0_cs3_bncr_value);
17f50f22 868 /* EBC Bank4 */
d1c3b275
SR		 869 mtebc(PB4AP, ebc0_cs4_bnap_value);
870 mtebc(PB4CR, ebc0_cs4_bncr_value);
17f50f22
SR		 871
872 return;
873}
874
875
876/*----------------------------------------------------------------------------+
877 | get_uart_configuration.
878 +----------------------------------------------------------------------------*/
879uart_config_nb_t get_uart_configuration(void)
8a316c9b 880{
c57c7980 881 return (L4);
17f50f22
SR		 882}
883
884/*----------------------------------------------------------------------------+
885 | set_phy_configuration_through_fpga => to EPLD
886 +----------------------------------------------------------------------------*/
887void set_phy_configuration_through_fpga(zmii_config_t config)
888{
889
890 unsigned long fpga_selection_reg;
891
892 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
893
894 switch(config)
895 {
f901a83b 896 case ZMII_CONFIGURATION_IS_MII:
17f50f22
SR		 897 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
898 break;
f901a83b 899 case ZMII_CONFIGURATION_IS_RMII:
17f50f22
SR		 900 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
901 break;
f901a83b 902 case ZMII_CONFIGURATION_IS_SMII:
17f50f22
SR		 903 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
904 break;
f901a83b
WD		 905 case ZMII_CONFIGURATION_UNKNOWN:
906 default:
17f50f22
SR		 907 break;
908 }
909 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
8a316c9b
SR		 910
911}
17f50f22
SR		 912
913/*----------------------------------------------------------------------------+
914 | scp_selection_in_fpga.
915 +----------------------------------------------------------------------------*/
916void scp_selection_in_fpga(void)
917{
918 unsigned long fpga_selection_2_reg;
919
920 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
921 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
922 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
923}
924
925/*----------------------------------------------------------------------------+
926 | iic1_selection_in_fpga.
927 +----------------------------------------------------------------------------*/
928void iic1_selection_in_fpga(void)
929{
930 unsigned long fpga_selection_2_reg;
931
932 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
933 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
934 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
935}
936
937/*----------------------------------------------------------------------------+
938 | dma_a_b_selection_in_fpga.
939 +----------------------------------------------------------------------------*/
940void dma_a_b_selection_in_fpga(void)
941{
942 unsigned long fpga_selection_2_reg;
943
944 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
945 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
946}
947
948/*----------------------------------------------------------------------------+
949 | dma_a_b_unselect_in_fpga.
950 +----------------------------------------------------------------------------*/
951void dma_a_b_unselect_in_fpga(void)
952{
953 unsigned long fpga_selection_2_reg;
954
955 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
956 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
957}
958
959/*----------------------------------------------------------------------------+
960 | dma_c_d_selection_in_fpga.
961 +----------------------------------------------------------------------------*/
962void dma_c_d_selection_in_fpga(void)
963{
964 unsigned long fpga_selection_2_reg;
965
966 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
967 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
968}
969
970/*----------------------------------------------------------------------------+
971 | dma_c_d_unselect_in_fpga.
972 +----------------------------------------------------------------------------*/
973void dma_c_d_unselect_in_fpga(void)
974{
975 unsigned long fpga_selection_2_reg;
976
977 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
978 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
979}
980
981/*----------------------------------------------------------------------------+
982 | usb2_device_selection_in_fpga.
983 +----------------------------------------------------------------------------*/
984void usb2_device_selection_in_fpga(void)
985{
986 unsigned long fpga_selection_1_reg;
987
988 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
989 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
990}
991
992/*----------------------------------------------------------------------------+
993 | usb2_device_reset_through_fpga.
994 +----------------------------------------------------------------------------*/
995void usb2_device_reset_through_fpga(void)
996{
997 /* Perform soft Reset pulse */
998 unsigned long fpga_reset_reg;
999 int i;
1000
1001 fpga_reset_reg = in8(FPGA_RESET_REG);
1002 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1003 for (i=0; i<500; i++)
1004 udelay(1000);
1005 out8(FPGA_RESET_REG,fpga_reset_reg);
1006}
1007
1008/*----------------------------------------------------------------------------+
1009 | usb2_host_selection_in_fpga.
1010 +----------------------------------------------------------------------------*/
1011void usb2_host_selection_in_fpga(void)
1012{
1013 unsigned long fpga_selection_1_reg;
1014
1015 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1016 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1017}
1018
1019/*----------------------------------------------------------------------------+
1020 | ndfc_selection_in_fpga.
1021 +----------------------------------------------------------------------------*/
1022void ndfc_selection_in_fpga(void)
1023{
1024 unsigned long fpga_selection_1_reg;
1025
1026 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1027 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
c57c7980 1028 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
17f50f22
SR		 1029 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1030}
1031
1032/*----------------------------------------------------------------------------+
1033 | uart_selection_in_fpga.
1034 +----------------------------------------------------------------------------*/
1035void uart_selection_in_fpga(uart_config_nb_t uart_config)
1036{
1037 /* FPGA register */
f901a83b 1038 unsigned char fpga_selection_3_reg;
17f50f22
SR		 1039
1040 /* Read FPGA Reagister */
1041 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1042
1043 switch (uart_config)
1044 {
1045 case L1:
1046 /* ----------------------------------------------------------------------- */
f901a83b 1047 /* L1 configuration: UART0 = 8 pins */
17f50f22
SR		 1048 /* ----------------------------------------------------------------------- */
1049 /* Configure FPGA */
f901a83b
WD		 1050 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1051 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
17f50f22
SR		 1052 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1053
1054 break;
1055
1056 case L2:
1057 /* ----------------------------------------------------------------------- */
f901a83b
WD		 1058 /* L2 configuration: UART0 = 4 pins */
1059 /* UART1 = 4 pins */
17f50f22
SR		 1060 /* ----------------------------------------------------------------------- */
1061 /* Configure FPGA */
f901a83b
WD		 1062 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1063 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
17f50f22
SR		 1064 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1065
1066 break;
1067
1068 case L3:
1069 /* ----------------------------------------------------------------------- */
f901a83b
WD		 1070 /* L3 configuration: UART0 = 4 pins */
1071 /* UART1 = 2 pins */
1072 /* UART2 = 2 pins */
17f50f22
SR		 1073 /* ----------------------------------------------------------------------- */
1074 /* Configure FPGA */
f901a83b
WD		 1075 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1076 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
17f50f22
SR		 1077 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1078 break;
1079
1080 case L4:
1081 /* Configure FPGA */
f901a83b
WD		 1082 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1083 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
17f50f22
SR		 1084 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1085
1086 break;
1087
1088 default:
1089 /* Unsupported UART configuration number */
1090 for (;;)
1091 ;
1092 break;
1093
1094 }
1095}
1096
1097
1098/*----------------------------------------------------------------------------+
1099 | init_default_gpio
1100 +----------------------------------------------------------------------------*/
d2f68006 1101void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22
SR		 1102{
1103 int i;
1104
1105 /* Init GPIO0 */
1106 for(i=0; i<GPIO_MAX; i++)
1107 {
f901a83b 1108 gpio_tab[GPIO0][i].add = GPIO0_BASE;
17f50f22
SR		 1109 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1110 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1111 }
1112
1113 /* Init GPIO1 */
1114 for(i=0; i<GPIO_MAX; i++)
1115 {
f901a83b 1116 gpio_tab[GPIO1][i].add = GPIO1_BASE;
17f50f22
SR		 1117 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1118 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1119 }
1120
1121 /* EBC_CS_N(5) - GPIO0_10 */
1122 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1123 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1124
1125 /* EBC_CS_N(4) - GPIO0_9 */
1126 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1127 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1128}
1129
1130/*----------------------------------------------------------------------------+
1131 | update_uart_ios
1132 +------------------------------------------------------------------------------
1133 |
1134 | Set UART Configuration in PowerPC440EP
1135 |
1136 | +---------------------------------------------------------------------+
f901a83b
WD		 1137 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1138 | | Number | Port Name | available | naming | CORE |
17f50f22 1139 | +-----------------+---------------+------------+--------+-------------+
f901a83b 1140 | | L1 | Port_A | 8 | UART | UART core 0 |
17f50f22 1141 | +-----------------+---------------+------------+--------+-------------+
f901a83b
WD		 1142 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1143 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
17f50f22 1144 | +-----------------+---------------+------------+--------+-------------+
f901a83b
WD		 1145 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1146 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1147 | | | Port_C | 2 | UART3 | UART core 2 |
17f50f22 1148 | +-----------------+---------------+------------+--------+-------------+
f901a83b
WD		 1149 | | | Port_A | 2 | UART1 | UART core 0 |
1150 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1151 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1152 | | | Port_D | 2 | UART4 | UART core 3 |
17f50f22
SR		 1153 | +-----------------+---------------+------------+--------+-------------+
1154 |
1155 | Involved GPIOs
1156 |
1157 | +------------------------------------------------------------------------------+
f901a83b 1158 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
17f50f22 1159 | +---------+------------------+-----+-----------------+-----+-------------+-----+
f901a83b
WD		 1160 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1161 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1162 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1163 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1164 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1165 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
17f50f22
SR		 1166 | +------------------------------------------------------------------------------+
1167 |
1168 |
1169 +----------------------------------------------------------------------------*/
1170
d2f68006 1171void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22
SR		 1172{
1173 switch (uart_config)
1174 {
1175 case L1:
1176 /* ----------------------------------------------------------------------- */
f901a83b 1177 /* L1 configuration: UART0 = 8 pins */
17f50f22
SR		 1178 /* ----------------------------------------------------------------------- */
1179 /* Update GPIO Configuration Table */
1180 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1181 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1182
1183 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1184 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1185
1186 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1187 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1188
1189 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1190 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1191
1192 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1193 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1194
1195 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1196 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1197
1198 break;
1199
1200 case L2:
1201 /* ----------------------------------------------------------------------- */
f901a83b
WD		 1202 /* L2 configuration: UART0 = 4 pins */
1203 /* UART1 = 4 pins */
17f50f22
SR		 1204 /* ----------------------------------------------------------------------- */
1205 /* Update GPIO Configuration Table */
1206 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1207 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1208
1209 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1210 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1211
1212 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1213 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1214
1215 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1216 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1217
1218 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1219 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1220
1221 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1222 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1223
1224 break;
1225
1226 case L3:
1227 /* ----------------------------------------------------------------------- */
f901a83b
WD		 1228 /* L3 configuration: UART0 = 4 pins */
1229 /* UART1 = 2 pins */
1230 /* UART2 = 2 pins */
17f50f22
SR		 1231 /* ----------------------------------------------------------------------- */
1232 /* Update GPIO Configuration Table */
1233 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1234 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1235
1236 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1237 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1238
1239 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1240 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1241
1242 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1243 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1244
1245 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1246 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1247
1248 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1249 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1250
1251 break;
1252
1253 case L4:
1254 /* ----------------------------------------------------------------------- */
f901a83b
WD		 1255 /* L4 configuration: UART0 = 2 pins */
1256 /* UART1 = 2 pins */
1257 /* UART2 = 2 pins */
1258 /* UART3 = 2 pins */
17f50f22
SR		 1259 /* ----------------------------------------------------------------------- */
1260 /* Update GPIO Configuration Table */
1261 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1262 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1263
1264 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1265 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1266
1267 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1268 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1269
1270 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1271 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1272
1273 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1274 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1275
1276 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1277 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1278
1279 break;
1280
1281 default:
1282 /* Unsupported UART configuration number */
1283 printf("ERROR - Unsupported UART configuration number.\n\n");
1284 for (;;)
1285 ;
1286 break;
1287
1288 }
1289
1290 /* Set input Selection Register on Alt_Receive for UART Input Core */
1291 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1292 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1293 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1294}
1295
1296/*----------------------------------------------------------------------------+
1297 | update_ndfc_ios(void).
1298 +----------------------------------------------------------------------------*/
d2f68006 1299void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1300{
f901a83b
WD		 1301 /* Update GPIO Configuration Table */
1302 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1303 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
17f50f22 1304
f901a83b 1305 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
17f50f22
SR		 1306 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1307
a471db07 1308#if 0
f901a83b 1309 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
17f50f22 1310 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
8a316c9b 1311#endif
17f50f22
SR		 1312}
1313
1314/*----------------------------------------------------------------------------+
1315 | update_zii_ios(void).
1316 +----------------------------------------------------------------------------*/
d2f68006 1317void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1318{
f901a83b
WD		 1319 /* Update GPIO Configuration Table */
1320 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1321 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
17f50f22 1322
f901a83b
WD		 1323 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1324 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
17f50f22 1325
f901a83b
WD		 1326 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1327 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
17f50f22 1328
f901a83b
WD		 1329 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1330 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
17f50f22 1331
f901a83b
WD		 1332 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1333 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
17f50f22 1334
f901a83b
WD		 1335 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1336 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
17f50f22 1337
f901a83b
WD		 1338 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1339 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
17f50f22 1340
f901a83b
WD		 1341 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1342 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
17f50f22 1343
f901a83b
WD		 1344 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1345 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
17f50f22 1346
f901a83b
WD		 1347 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1348 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
17f50f22 1349
f901a83b
WD		 1350 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1351 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
17f50f22 1352
f901a83b
WD		 1353 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1354 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
17f50f22 1355
f901a83b
WD		 1356 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1357 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
17f50f22 1358
f901a83b
WD		 1359 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1360 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
17f50f22
SR		 1361
1362}
1363
1364/*----------------------------------------------------------------------------+
1365 | update_uic_0_3_irq_ios().
1366 +----------------------------------------------------------------------------*/
d2f68006 1367void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1368{
f901a83b 1369 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
17f50f22
SR		 1370 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1371
f901a83b 1372 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
17f50f22
SR		 1373 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1374
f901a83b 1375 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
17f50f22
SR		 1376 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1377
f901a83b 1378 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
17f50f22
SR		 1379 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1380}
1381
1382/*----------------------------------------------------------------------------+
1383 | update_uic_4_9_irq_ios().
1384 +----------------------------------------------------------------------------*/
d2f68006 1385void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1386{
f901a83b 1387 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
17f50f22
SR		 1388 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1389
f901a83b 1390 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
17f50f22
SR		 1391 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1392
f901a83b 1393 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
17f50f22
SR		 1394 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1395
f901a83b 1396 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
17f50f22
SR		 1397 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1398
f901a83b 1399 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
17f50f22
SR		 1400 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1401}
1402
1403/*----------------------------------------------------------------------------+
1404 | update_dma_a_b_ios().
1405 +----------------------------------------------------------------------------*/
d2f68006 1406void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1407{
f901a83b 1408 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
17f50f22
SR		 1409 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1410
f901a83b 1411 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
17f50f22
SR		 1412 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1413
f901a83b 1414 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
17f50f22
SR		 1415 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1416
f901a83b 1417 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
17f50f22
SR		 1418 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1419
f901a83b 1420 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
17f50f22
SR		 1421 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1422}
1423
1424/*----------------------------------------------------------------------------+
1425 | update_dma_c_d_ios().
1426 +----------------------------------------------------------------------------*/
d2f68006 1427void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1428{
f901a83b 1429 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
17f50f22
SR		 1430 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1431
f901a83b 1432 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
17f50f22
SR		 1433 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1434
f901a83b 1435 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
17f50f22
SR		 1436 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1437
f901a83b 1438 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
17f50f22
SR		 1439 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1440
f901a83b 1441 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
17f50f22
SR		 1442 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1443
f901a83b 1444 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
17f50f22
SR		 1445 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1446
1447}
1448
1449/*----------------------------------------------------------------------------+
1450 | update_ebc_master_ios().
1451 +----------------------------------------------------------------------------*/
d2f68006 1452void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1453{
f901a83b 1454 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
17f50f22
SR		 1455 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1456
f901a83b 1457 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
17f50f22
SR		 1458 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1459
f901a83b 1460 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
17f50f22
SR		 1461 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1462
f901a83b 1463 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
17f50f22
SR		 1464 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1465}
1466
1467/*----------------------------------------------------------------------------+
1468 | update_usb2_device_ios().
1469 +----------------------------------------------------------------------------*/
d2f68006 1470void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1471{
f901a83b 1472 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
17f50f22
SR		 1473 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1474
f901a83b 1475 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
17f50f22
SR		 1476 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1477
f901a83b 1478 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
17f50f22
SR		 1479 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1480
f901a83b 1481 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
17f50f22
SR		 1482 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1483
f901a83b 1484 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
17f50f22
SR		 1485 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1486
f901a83b 1487 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
17f50f22
SR		 1488 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1489
f901a83b 1490 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
17f50f22
SR		 1491 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1492
f901a83b 1493 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
17f50f22
SR		 1494 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1495
1496}
1497
1498/*----------------------------------------------------------------------------+
1499 | update_pci_patch_ios().
1500 +----------------------------------------------------------------------------*/
d2f68006 1501void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1502{
f901a83b 1503 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
17f50f22
SR		 1504 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1505}
1506
1507/*----------------------------------------------------------------------------+
d2f68006
EO		 1508 | set_chip_gpio_configuration(unsigned char gpio_core,
1509 | gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22
SR		 1510 | Put the core impacted by clock modification and sharing in reset.
1511 | Config the select registers to resolve the sharing depending of the config.
1512 | Configure the GPIO registers.
1513 |
1514 +----------------------------------------------------------------------------*/
d2f68006 1515void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22
SR		 1516{
1517 unsigned char i=0, j=0, reg_offset = 0;
1518 unsigned long gpio_reg, gpio_core_add;
1519
1520 /* GPIO config of the GPIOs 0 to 31 */
1521 for (i=0; i<GPIO_MAX; i++, j++)
1522 {
1523 if (i == GPIO_MAX/2)
1524 {
1525 reg_offset = 4;
1526 j = i-16;
1527 }
1528
1529 gpio_core_add = gpio_tab[gpio_core][i].add;
1530
1531 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1532 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1533 {
1534 switch (gpio_tab[gpio_core][i].alt_nb)
1535 {
1536 case GPIO_SEL:
1537 break;
1538
1539 case GPIO_ALT1:
1540 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1541 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1542 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1543 break;
1544
1545 case GPIO_ALT2:
1546 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1547 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1548 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1549 break;
1550
1551 case GPIO_ALT3:
1552 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1553 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1554 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1555 break;
1556 }
1557 }
1558 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1559 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1560 {
1561
1562 switch (gpio_tab[gpio_core][i].alt_nb)
1563 {
1564 case GPIO_SEL:
1565 break;
1566 case GPIO_ALT1:
1567 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1568 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1569 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1570 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1571 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1572 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1573 break;
1574 case GPIO_ALT2:
1575 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1576 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1577 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1578 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1579 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1580 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1581 break;
1582 case GPIO_ALT3:
1583 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1584 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1585 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1586 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1587 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1588 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1589 break;
1590 }
1591 }
1592 }
1593}
1594
1595/*----------------------------------------------------------------------------+
1596 | force_bup_core_selection.
1597 +----------------------------------------------------------------------------*/
1598void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1599{
1600 /* Pointer invalid */
1601 if (core_select_P == NULL)
1602 {
1603 printf("Configuration invalid pointer 1\n");
1604 for (;;)
1605 ;
1606 }
1607
1608 /* L4 Selection */
f901a83b
WD		 1609 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1610 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1611 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1612 *(core_select_P+UART_CORE3) = CORE_SELECTED;
17f50f22
SR		 1613
1614 /* RMII Selection */
f901a83b 1615 *(core_select_P+RMII_SEL) = CORE_SELECTED;
17f50f22
SR		 1616
1617 /* External Interrupt 0-9 selection */
f901a83b
WD		 1618 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1619 *(core_select_P+UIC_4_9) = CORE_SELECTED;
17f50f22 1620
c57c7980
SR		 1621 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1622 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1623 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
f901a83b 1624 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
17f50f22 1625
c57c7980
SR		 1626 if (is_nand_selected()) {
1627 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1628 }
1629
17f50f22
SR		 1630 *config_val_P = CONFIG_IS_VALID;
1631
1632}
1633
1634/*----------------------------------------------------------------------------+
1635 | configure_ppc440ep_pins.
1636 +----------------------------------------------------------------------------*/
1637void configure_ppc440ep_pins(void)
1638{
1639 uart_config_nb_t uart_configuration;
1640 config_validity_t config_val = CONFIG_IS_INVALID;
1641
1642 /* Create Core Selection Table */
1643 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1644 {
f901a83b
WD		 1645 CORE_NOT_SELECTED, /* IIC_CORE, */
1646 CORE_NOT_SELECTED, /* SPC_CORE, */
1647 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1648 CORE_NOT_SELECTED, /* UIC_4_9, */
1649 CORE_NOT_SELECTED, /* USB2_HOST, */
1650 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1651 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1652 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1653 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1654 CORE_NOT_SELECTED, /* EBC_MASTER, */
1655 CORE_NOT_SELECTED, /* NAND_FLASH, */
1656 CORE_NOT_SELECTED, /* UART_CORE0, */
1657 CORE_NOT_SELECTED, /* UART_CORE1, */
1658 CORE_NOT_SELECTED, /* UART_CORE2, */
1659 CORE_NOT_SELECTED, /* UART_CORE3, */
1660 CORE_NOT_SELECTED, /* MII_SEL, */
1661 CORE_NOT_SELECTED, /* RMII_SEL, */
1662 CORE_NOT_SELECTED, /* SMII_SEL, */
1663 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1664 CORE_NOT_SELECTED, /* UIC_0_3 */
1665 CORE_NOT_SELECTED, /* USB1_HOST */
1666 CORE_NOT_SELECTED /* PCI_PATCH */
17f50f22
SR		 1667 };
1668
d2f68006 1669 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
17f50f22
SR		 1670
1671 /* Table Default Initialisation + FPGA Access */
d2f68006
EO		 1672 init_default_gpio(gpio_tab);
1673 set_chip_gpio_configuration(GPIO0, gpio_tab);
1674 set_chip_gpio_configuration(GPIO1, gpio_tab);
17f50f22
SR		 1675
1676 /* Update Table */
1677 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1678#if 0 /* test-only */
1679 /* If we are running PIBS 1, force known configuration */
1680 update_core_selection_table(ppc440ep_core_selection, &config_val);
1681#endif
1682
1683 /*----------------------------------------------------------------------------+
1684 | SDR + ios table update + fpga initialization
1685 +----------------------------------------------------------------------------*/
f901a83b
WD		 1686 unsigned long sdr0_pfc1 = 0;
1687 unsigned long sdr0_usb0 = 0;
1688 unsigned long sdr0_mfr = 0;
17f50f22
SR		 1689
1690 /* PCI Always selected */
1691
1692 /* I2C Selection */
1693 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1694 {
1695 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1696 iic1_selection_in_fpga();
1697 }
1698
1699 /* SCP Selection */
1700 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1701 {
1702 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1703 scp_selection_in_fpga();
1704 }
1705
1706 /* UIC 0:3 Selection */
1707 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1708 {
d2f68006 1709 update_uic_0_3_irq_ios(gpio_tab);
17f50f22
SR		 1710 dma_a_b_unselect_in_fpga();
1711 }
1712
1713 /* UIC 4:9 Selection */
1714 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1715 {
1716 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
d2f68006 1717 update_uic_4_9_irq_ios(gpio_tab);
17f50f22
SR		 1718 }
1719
1720 /* DMA AB Selection */
1721 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1722 {
1723 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
d2f68006 1724 update_dma_a_b_ios(gpio_tab);
17f50f22
SR		 1725 dma_a_b_selection_in_fpga();
1726 }
1727
1728 /* DMA CD Selection */
1729 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1730 {
d2f68006 1731 update_dma_c_d_ios(gpio_tab);
17f50f22
SR		 1732 dma_c_d_selection_in_fpga();
1733 }
1734
1735 /* EBC Master Selection */
1736 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1737 {
1738 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1739 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
d2f68006 1740 update_ebc_master_ios(gpio_tab);
17f50f22
SR		 1741 }
1742
1743 /* PCI Patch Enable */
1744 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1745 {
1746 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
d2f68006 1747 update_pci_patch_ios(gpio_tab);
17f50f22
SR		 1748 }
1749
1750 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1751 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1752 {
1753 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1754 printf("Invalid configuration => USB2 Host selected\n");
1755 for (;;)
1756 ;
1757 /*usb2_host_selection_in_fpga(); */
1758 }
1759
1760 /* USB2.0 Device Selection */
1761 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1762 {
d2f68006 1763 update_usb2_device_ios(gpio_tab);
17f50f22
SR		 1764 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1765 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1766
d1c3b275 1767 mfsdr(SDR0_USB0, sdr0_usb0);
17f50f22
SR		 1768 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1769 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
d1c3b275 1770 mtsdr(SDR0_USB0, sdr0_usb0);
17f50f22
SR		 1771
1772 usb2_device_selection_in_fpga();
1773 }
1774
1775 /* USB1.1 Device Selection */
1776 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1777 {
d1c3b275 1778 mfsdr(SDR0_USB0, sdr0_usb0);
17f50f22
SR		 1779 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1780 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
d1c3b275 1781 mtsdr(SDR0_USB0, sdr0_usb0);
17f50f22
SR		 1782 }
1783
1784 /* USB1.1 Host Selection */
1785 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1786 {
d1c3b275 1787 mfsdr(SDR0_USB0, sdr0_usb0);
17f50f22
SR		 1788 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1789 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
d1c3b275 1790 mtsdr(SDR0_USB0, sdr0_usb0);
17f50f22
SR		 1791 }
1792
1793 /* NAND Flash Selection */
1794 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1795 {
d2f68006 1796 update_ndfc_ios(gpio_tab);
17f50f22 1797
a471db07 1798#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
d1c3b275 1799 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
f901a83b
WD		 1800 SDR0_CUST0_NDFC_ENABLE |
1801 SDR0_CUST0_NDFC_BW_8_BIT |
1802 SDR0_CUST0_NDFC_ARE_MASK |
c57c7980
SR		 1803 SDR0_CUST0_CHIPSELGAT_EN1 |
1804 SDR0_CUST0_CHIPSELGAT_EN2);
a471db07 1805#else
d1c3b275 1806 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
a471db07
SR		 1807 SDR0_CUST0_NDFC_ENABLE |
1808 SDR0_CUST0_NDFC_BW_8_BIT |
1809 SDR0_CUST0_NDFC_ARE_MASK |
1810 SDR0_CUST0_CHIPSELGAT_EN0 |
1811 SDR0_CUST0_CHIPSELGAT_EN2);
1812#endif
17f50f22
SR		 1813
1814 ndfc_selection_in_fpga();
1815 }
1816 else
1817 {
1818 /* Set Mux on EMAC */
d1c3b275 1819 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
17f50f22
SR		 1820 }
1821
1822 /* MII Selection */
1823 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1824 {
d2f68006 1825 update_zii_ios(gpio_tab);
d1c3b275 1826 mfsdr(SDR0_MFR, sdr0_mfr);
17f50f22 1827 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
d1c3b275 1828 mtsdr(SDR0_MFR, sdr0_mfr);
17f50f22
SR		 1829
1830 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
1831 }
1832
1833 /* RMII Selection */
1834 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
1835 {
d2f68006 1836 update_zii_ios(gpio_tab);
d1c3b275 1837 mfsdr(SDR0_MFR, sdr0_mfr);
17f50f22 1838 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
d1c3b275 1839 mtsdr(SDR0_MFR, sdr0_mfr);
17f50f22
SR		 1840
1841 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
1842 }
1843
1844 /* SMII Selection */
1845 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
1846 {
d2f68006 1847 update_zii_ios(gpio_tab);
d1c3b275 1848 mfsdr(SDR0_MFR, sdr0_mfr);
17f50f22 1849 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
d1c3b275 1850 mtsdr(SDR0_MFR, sdr0_mfr);
17f50f22
SR		 1851
1852 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
1853 }
1854
1855 /* UART Selection */
1856 uart_configuration = get_uart_configuration();
1857 switch (uart_configuration)
1858 {
f901a83b 1859 case L1: /* L1 Selection */
17f50f22
SR		 1860 /* UART0 8 pins Only */
1861 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
f901a83b 1862 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
17f50f22
SR		 1863 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
1864 break;
f901a83b 1865 case L2: /* L2 Selection */
17f50f22
SR		 1866 /* UART0 and UART1 4 pins */
1867 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1868 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1869 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1870 break;
f901a83b 1871 case L3: /* L3 Selection */
17f50f22
SR		 1872 /* UART0 4 pins, UART1 and UART2 2 pins */
1873 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1874 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1875 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1876 break;
f901a83b 1877 case L4: /* L4 Selection */
17f50f22
SR		 1878 /* UART0, UART1, UART2 and UART3 2 pins */
1879 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
1880 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1881 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1882 break;
1883 }
d2f68006 1884 update_uart_ios(uart_configuration, gpio_tab);
17f50f22
SR		 1885
1886 /* UART Selection in all cases */
1887 uart_selection_in_fpga(uart_configuration);
1888
1889 /* Packet Reject Function Available */
1890 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
1891 {
1892 /* Set UPR Bit in SDR0_PFC1 Register */
1893 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
1894 }
1895
1896 /* Packet Reject Function Enable */
1897 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
1898 {
d1c3b275 1899 mfsdr(SDR0_MFR, sdr0_mfr);
17f50f22 1900 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
d1c3b275 1901 mtsdr(SDR0_MFR, sdr0_mfr);
17f50f22
SR		 1902 }
1903
1904 /* Perform effective access to hardware */
d1c3b275 1905 mtsdr(SDR0_PFC1, sdr0_pfc1);
d2f68006
EO		 1906 set_chip_gpio_configuration(GPIO0, gpio_tab);
1907 set_chip_gpio_configuration(GPIO1, gpio_tab);
17f50f22
SR		 1908
1909 /* USB2.0 Device Reset must be done after GPIO setting */
1910 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1911 usb2_device_reset_through_fpga();
1912
1913}
"Das U-Boot" Source Tree