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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / amcc / bamboo / bamboo.c
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8a316c9b 1/*
a471db07 2 * (C) Copyright 2005-2007
8a316c9b
SR		 3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
f901a83b 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8a316c9b
SR		 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
0d974d52 26#include <asm/gpio.h>
8a316c9b 27#include <spd_sdram.h>
17f50f22
SR		 28#include <ppc440.h>
29#include "bamboo.h"
8a316c9b 30
17f50f22
SR		 31void ext_bus_cntlr_init(void);
32void configure_ppc440ep_pins(void);
c57c7980 33int is_nand_selected(void);
8a316c9b 34
d2f68006
EO		 35#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
36/*************************************************************************
37 *
38 * Bamboo has one bank onboard sdram (plus DIMM)
39 *
40 * Fixed memory is composed of :
41 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
42 * 13 row add bits, 10 column add bits (but 12 row used only).
43 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
44 * 12 row add bits, 10 column add bits.
45 * Prepare a subset (only the used ones) of SPD data
46 *
47 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
48 * the corresponding bank is divided by 2 due to number of Row addresses
49 * 12 in the ECC module
50 *
51 * Assumes: 64 MB, ECC, non-registered
52 * PLB @ 133 MHz
53 *
54 ************************************************************************/
55const unsigned char cfg_simulate_spd_eeprom[128] = {
56 0x80, /* number of SPD bytes used: 128 */
57 0x08, /* total number bytes in SPD device = 256 */
58 0x07, /* DDR ram */
59#ifdef CONFIG_DDR_ECC
60 0x0C, /* num Row Addr: 12 */
61#else
62 0x0D, /* num Row Addr: 13 */
63#endif
64 0x09, /* numColAddr: 9 */
65 0x01, /* numBanks: 1 */
66 0x20, /* Module data width: 32 bits */
67 0x00, /* Module data width continued: +0 */
68 0x04, /* 2.5 Volt */
69 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
9f798766 70 0x00, /* SDRAM Access from clock */
d2f68006
EO		 71#ifdef CONFIG_DDR_ECC
72 0x02, /* ECC ON : 02 OFF : 00 */
73#else
74 0x00, /* ECC ON : 02 OFF : 00 */
75#endif
9f798766 76 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
d2f68006
EO		 77 0,
78 0,
79 0x01, /* wcsbc = 1 */
80 0,
81 0,
82 0x0C, /* casBit (2,2.5) */
83 0,
84 0,
85 0x00, /* not registered: 0 registered : 0x02*/
86 0,
87 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
88 0,
89 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
90 0,
91 0x50, /* tRpNs = 20 ns */
92 0,
93 0x50, /* tRcdNs = 20 ns */
94 45, /* tRasNs */
95#ifdef CONFIG_DDR_ECC
96 0x08, /* bankSizeID: 32MB */
97#else
98 0x10, /* bankSizeID: 64MB */
99#endif
100 0,
101 0,
102 0,
103 0,
104 0,
105 0,
106 0,
107 0,
108 0,
109 0,
110 0,
111 0,
112 0,
113 0,
114 0,
115 0,
116 0,
117 0,
118 0,
119 0,
120 0,
121 0,
122 0,
123 0,
124 0,
125 0,
126 0,
127 0,
128 0,
129 0,
130 0,
131 0,
132 0,
133 0,
134 0,
135 0,
136 0,
137 0,
138 0,
139 0,
140 0,
141 0,
142 0,
143 0,
144 0,
145 0,
146 0,
147 0,
148 0,
149 0,
150 0,
151 0,
152 0,
153 0,
154 0,
155 0,
156 0,
157 0,
158 0,
159 0,
160 0,
161 0,
162 0,
163 0,
164 0,
165 0,
166 0,
167 0,
168 0,
169 0,
170 0,
171 0,
172 0,
173 0,
174 0,
175 0,
176 0,
177 0,
178 0,
179 0,
180 0,
181 0,
182 0,
183 0,
184 0,
185 0,
186 0,
187 0,
188 0,
189 0,
190 0,
191 0,
192 0,
193 0,
194 0,
195 0
196};
197#endif
fd49bf02 198
17f50f22 199#if 0
f901a83b
WD		 200{ /* GPIO Alternate1 Alternate2 Alternate3 */
201 {
202 /* GPIO Core 0 */
203 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
204 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
205 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
206 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
207 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
208 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
209 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
210 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
211 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
212 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
213 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
214 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
215 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
216 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
217 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
218 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
219 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
220 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
221 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
222 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
223 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
224 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
225 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
226 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
227 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
228 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
229 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
230 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
231 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
232 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
233 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
234 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
235 },
236 {
237 /* GPIO Core 1 */
238 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
239 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
240 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
241 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
242 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
243 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
244 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
245 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
246 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
247 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
248 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
249 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
250 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
251 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
252 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
253 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
254 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
255 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
256 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
257 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
258 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
259 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
260 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
261 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
262 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
263 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
264 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
265 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
266 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
267 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
268 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
269 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
270 }
17f50f22
SR		 271};
272#endif
8a316c9b 273
17f50f22
SR		 274/*----------------------------------------------------------------------------+
275 | EBC Devices Characteristics
f901a83b
WD		 276 | Peripheral Bank Access Parameters - EBC0_BnAP
277 | Peripheral Bank Configuration Register - EBC0_BnCR
17f50f22
SR		 278 +----------------------------------------------------------------------------*/
279/* Small Flash */
f901a83b
WD		 280#define EBC0_BNAP_SMALL_FLASH \
281 EBC0_BNAP_BME_DISABLED | \
282 EBC0_BNAP_TWT_ENCODE(6) | \
53677ef1
WD		 283 EBC0_BNAP_CSN_ENCODE(0) | \
284 EBC0_BNAP_OEN_ENCODE(1) | \
285 EBC0_BNAP_WBN_ENCODE(1) | \
286 EBC0_BNAP_WBF_ENCODE(3) | \
287 EBC0_BNAP_TH_ENCODE(1) | \
288 EBC0_BNAP_RE_ENABLED | \
289 EBC0_BNAP_SOR_DELAYED | \
290 EBC0_BNAP_BEM_WRITEONLY | \
17f50f22 291 EBC0_BNAP_PEN_DISABLED
8a316c9b 292
f901a83b 293#define EBC0_BNCR_SMALL_FLASH_CS0 \
53677ef1
WD		 294 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
295 EBC0_BNCR_BS_1MB | \
296 EBC0_BNCR_BU_RW | \
17f50f22 297 EBC0_BNCR_BW_8BIT
8a316c9b 298
f901a83b 299#define EBC0_BNCR_SMALL_FLASH_CS4 \
53677ef1
WD		 300 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
301 EBC0_BNCR_BS_1MB | \
302 EBC0_BNCR_BU_RW | \
c57c7980 303 EBC0_BNCR_BW_8BIT
17f50f22
SR		 304
305/* Large Flash or SRAM */
f901a83b 306#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
53677ef1
WD		 307 EBC0_BNAP_BME_DISABLED | \
308 EBC0_BNAP_TWT_ENCODE(8) | \
309 EBC0_BNAP_CSN_ENCODE(0) | \
310 EBC0_BNAP_OEN_ENCODE(1) | \
311 EBC0_BNAP_WBN_ENCODE(1) | \
312 EBC0_BNAP_WBF_ENCODE(1) | \
313 EBC0_BNAP_TH_ENCODE(2) | \
314 EBC0_BNAP_SOR_DELAYED | \
315 EBC0_BNAP_BEM_RW | \
17f50f22
SR		 316 EBC0_BNAP_PEN_DISABLED
317
53677ef1
WD		 318#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
319 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
320 EBC0_BNCR_BS_8MB | \
321 EBC0_BNCR_BU_RW | \
17f50f22
SR		 322 EBC0_BNCR_BW_16BIT
323
324
53677ef1
WD		 325#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
326 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
327 EBC0_BNCR_BS_8MB | \
328 EBC0_BNCR_BU_RW | \
17f50f22 329 EBC0_BNCR_BW_16BIT
8a316c9b 330
17f50f22 331/* NVRAM - FPGA */
f901a83b 332#define EBC0_BNAP_NVRAM_FPGA \
53677ef1
WD		 333 EBC0_BNAP_BME_DISABLED | \
334 EBC0_BNAP_TWT_ENCODE(9) | \
335 EBC0_BNAP_CSN_ENCODE(0) | \
336 EBC0_BNAP_OEN_ENCODE(1) | \
337 EBC0_BNAP_WBN_ENCODE(1) | \
338 EBC0_BNAP_WBF_ENCODE(0) | \
339 EBC0_BNAP_TH_ENCODE(2) | \
340 EBC0_BNAP_RE_ENABLED | \
341 EBC0_BNAP_SOR_DELAYED | \
342 EBC0_BNAP_BEM_WRITEONLY | \
17f50f22 343 EBC0_BNAP_PEN_DISABLED
8a316c9b 344
f901a83b 345#define EBC0_BNCR_NVRAM_FPGA_CS5 \
53677ef1
WD		 346 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
347 EBC0_BNCR_BS_1MB | \
348 EBC0_BNCR_BU_RW | \
17f50f22 349 EBC0_BNCR_BW_8BIT
8a316c9b 350
17f50f22 351/* Nand Flash */
f901a83b 352#define EBC0_BNAP_NAND_FLASH \
53677ef1
WD		 353 EBC0_BNAP_BME_DISABLED | \
354 EBC0_BNAP_TWT_ENCODE(3) | \
355 EBC0_BNAP_CSN_ENCODE(0) | \
356 EBC0_BNAP_OEN_ENCODE(0) | \
357 EBC0_BNAP_WBN_ENCODE(0) | \
358 EBC0_BNAP_WBF_ENCODE(0) | \
359 EBC0_BNAP_TH_ENCODE(1) | \
360 EBC0_BNAP_RE_ENABLED | \
361 EBC0_BNAP_SOR_NOT_DELAYED | \
362 EBC0_BNAP_BEM_RW | \
17f50f22
SR		 363 EBC0_BNAP_PEN_DISABLED
364
365
f901a83b 366#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
17f50f22
SR		 367
368/* NAND0 */
f901a83b 369#define EBC0_BNCR_NAND_FLASH_CS1 \
53677ef1
WD		 370 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
371 EBC0_BNCR_BS_1MB | \
372 EBC0_BNCR_BU_RW | \
17f50f22
SR		 373 EBC0_BNCR_BW_32BIT
374/* NAND1 - Bank2 */
f901a83b 375#define EBC0_BNCR_NAND_FLASH_CS2 \
53677ef1
WD		 376 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
377 EBC0_BNCR_BS_1MB | \
378 EBC0_BNCR_BU_RW | \
17f50f22
SR		 379 EBC0_BNCR_BW_32BIT
380
381/* NAND1 - Bank3 */
f901a83b 382#define EBC0_BNCR_NAND_FLASH_CS3 \
53677ef1
WD		 383 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
384 EBC0_BNCR_BS_1MB | \
385 EBC0_BNCR_BU_RW | \
17f50f22
SR		 386 EBC0_BNCR_BW_32BIT
387
388int board_early_init_f(void)
389{
390 ext_bus_cntlr_init();
8a316c9b
SR		 391
392 /*--------------------------------------------------------------------
393 * Setup the interrupt controller polarities, triggers, etc.
394 *-------------------------------------------------------------------*/
395 mtdcr(uic0sr, 0xffffffff); /* clear all */
396 mtdcr(uic0er, 0x00000000); /* disable all */
397 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
398 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
399 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
400 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
401 mtdcr(uic0sr, 0xffffffff); /* clear all */
402
403 mtdcr(uic1sr, 0xffffffff); /* clear all */
404 mtdcr(uic1er, 0x00000000); /* disable all */
405 mtdcr(uic1cr, 0x00000000); /* all non-critical */
406 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
407 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
408 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
409 mtdcr(uic1sr, 0xffffffff); /* clear all */
410
411 /*--------------------------------------------------------------------
412 * Setup the GPIO pins
413 *-------------------------------------------------------------------*/
17f50f22
SR		 414 out32(GPIO0_OSRL, 0x00000400);
415 out32(GPIO0_OSRH, 0x00000000);
416 out32(GPIO0_TSRL, 0x00000400);
417 out32(GPIO0_TSRH, 0x00000000);
418 out32(GPIO0_ISR1L, 0x00000000);
419 out32(GPIO0_ISR1H, 0x00000000);
420 out32(GPIO0_ISR2L, 0x00000000);
421 out32(GPIO0_ISR2H, 0x00000000);
422 out32(GPIO0_ISR3L, 0x00000000);
423 out32(GPIO0_ISR3H, 0x00000000);
8a316c9b 424
17f50f22
SR		 425 out32(GPIO1_OSRL, 0x0C380000);
426 out32(GPIO1_OSRH, 0x00000000);
427 out32(GPIO1_TSRL, 0x0C380000);
428 out32(GPIO1_TSRH, 0x00000000);
429 out32(GPIO1_ISR1L, 0x0FC30000);
430 out32(GPIO1_ISR1H, 0x00000000);
431 out32(GPIO1_ISR2L, 0x0C010000);
432 out32(GPIO1_ISR2H, 0x00000000);
433 out32(GPIO1_ISR3L, 0x01400000);
434 out32(GPIO1_ISR3H, 0x00000000);
8a316c9b 435
17f50f22 436 configure_ppc440ep_pins();
8a316c9b
SR		 437
438 return 0;
439}
440
441int checkboard(void)
442{
3d9569b2 443 char *s = getenv("serial#");
8a316c9b
SR		 444
445 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
446 if (s != NULL) {
447 puts(", serial# ");
448 puts(s);
449 }
450 putc('\n');
451
8a316c9b
SR		 452 return (0);
453}
454
8a316c9b 455
9973e3c6 456phys_size_t initdram (int board_type)
8a316c9b 457{
a471db07
SR		 458#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
459 long dram_size;
17f50f22 460
d19206b9 461 dram_size = spd_sdram();
17f50f22
SR		 462
463 return dram_size;
a471db07 464#else
6d0f6bcf 465 return CONFIG_SYS_MBYTES_SDRAM << 20;
a471db07 466#endif
8a316c9b
SR		 467}
468
8a316c9b
SR		 469/*************************************************************************
470 * pci_pre_init
471 *
472 * This routine is called just prior to registering the hose and gives
473 * the board the opportunity to check things. Returning a value of zero
474 * indicates that things are bad & PCI initialization should be aborted.
475 *
476 * Different boards may wish to customize the pci controller structure
477 * (add regions, override default access routines, etc) or perform
478 * certain pre-initialization actions.
479 *
480 ************************************************************************/
466fff1a 481#if defined(CONFIG_PCI)
8a316c9b
SR		 482int pci_pre_init(struct pci_controller *hose)
483{
8a316c9b
SR		 484 unsigned long addr;
485
8a316c9b
SR		 486 /*-------------------------------------------------------------------------+
487 | Set priority for all PLB3 devices to 0.
488 | Set PLB3 arbiter to fair mode.
489 +-------------------------------------------------------------------------*/
490 mfsdr(sdr_amp1, addr);
491 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
492 addr = mfdcr(plb3_acr);
493 mtdcr(plb3_acr, addr | 0x80000000);
494
495 /*-------------------------------------------------------------------------+
496 | Set priority for all PLB4 devices to 0.
497 +-------------------------------------------------------------------------*/
498 mfsdr(sdr_amp0, addr);
499 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
500 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
501 mtdcr(plb4_acr, addr);
502
503 /*-------------------------------------------------------------------------+
504 | Set Nebula PLB4 arbiter to fair mode.
505 +-------------------------------------------------------------------------*/
506 /* Segment0 */
507 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
508 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
509 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
510 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
511 mtdcr(plb0_acr, addr);
512
513 /* Segment1 */
514 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
515 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
516 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
517 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
518 mtdcr(plb1_acr, addr);
519
520 return 1;
521}
466fff1a 522#endif /* defined(CONFIG_PCI) */
8a316c9b
SR		 523
524/*************************************************************************
525 * pci_target_init
526 *
527 * The bootstrap configuration provides default settings for the pci
528 * inbound map (PIM). But the bootstrap config choices are limited and
529 * may not be sufficient for a given board.
530 *
531 ************************************************************************/
6d0f6bcf 532#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
8a316c9b
SR		 533void pci_target_init(struct pci_controller *hose)
534{
535 /*--------------------------------------------------------------------------+
536 * Set up Direct MMIO registers
537 *--------------------------------------------------------------------------*/
538 /*--------------------------------------------------------------------------+
539 | PowerPC440 EP PCI Master configuration.
540 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
541 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
542 | Use byte reversed out routines to handle endianess.
543 | Make this region non-prefetchable.
544 +--------------------------------------------------------------------------*/
545 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
6d0f6bcf
JCPV		 546 out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
547 out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
8a316c9b
SR		 548 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
549 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
550
551 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
6d0f6bcf
JCPV		 552 out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
553 out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
8a316c9b
SR		 554 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
555 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
556
557 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
558 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
559 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
560 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
561
562 /*--------------------------------------------------------------------------+
563 * Set up Configuration registers
564 *--------------------------------------------------------------------------*/
565
566 /* Program the board's subsystem id/vendor id */
567 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
6d0f6bcf
JCPV		 568 CONFIG_SYS_PCI_SUBSYS_VENDORID);
569 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
8a316c9b
SR		 570
571 /* Configure command register as bus master */
572 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
573
574 /* 240nS PCI clock */
575 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
576
577 /* No error reporting */
578 pci_write_config_word(0, PCI_ERREN, 0);
579
580 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
581
582}
6d0f6bcf 583#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
8a316c9b
SR		 584
585/*************************************************************************
586 * pci_master_init
587 *
588 ************************************************************************/
6d0f6bcf 589#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
8a316c9b
SR		 590void pci_master_init(struct pci_controller *hose)
591{
592 unsigned short temp_short;
593
594 /*--------------------------------------------------------------------------+
595 | Write the PowerPC440 EP PCI Configuration regs.
596 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
597 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
598 +--------------------------------------------------------------------------*/
599 pci_read_config_word(0, PCI_COMMAND, &temp_short);
600 pci_write_config_word(0, PCI_COMMAND,
601 temp_short | PCI_COMMAND_MASTER |
602 PCI_COMMAND_MEMORY);
603}
6d0f6bcf 604#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
8a316c9b
SR		 605
606/*************************************************************************
607 * is_pci_host
608 *
609 * This routine is called to determine if a pci scan should be
610 * performed. With various hardware environments (especially cPCI and
611 * PPMC) it's insufficient to depend on the state of the arbiter enable
612 * bit in the strap register, or generic host/adapter assumptions.
613 *
614 * Rather than hard-code a bad assumption in the general 440 code, the
615 * 440 pci code requires the board to decide at runtime.
616 *
617 * Return 0 for adapter mode, non-zero for host (monarch) mode.
618 *
619 *
620 ************************************************************************/
621#if defined(CONFIG_PCI)
622int is_pci_host(struct pci_controller *hose)
623{
624 /* Bamboo is always configured as host. */
625 return (1);
626}
627#endif /* defined(CONFIG_PCI) */
628
17f50f22
SR		 629/*----------------------------------------------------------------------------+
630 | is_powerpc440ep_pass1.
631 +----------------------------------------------------------------------------*/
632int is_powerpc440ep_pass1(void)
633{
634 unsigned long pvr;
635
636 pvr = get_pvr();
637
638 if (pvr == PVR_POWERPC_440EP_PASS1)
639 return TRUE;
640 else if (pvr == PVR_POWERPC_440EP_PASS2)
641 return FALSE;
642 else {
643 printf("brdutil error 3\n");
644 for (;;)
645 ;
646 }
647
648 return(FALSE);
649}
650
651/*----------------------------------------------------------------------------+
652 | is_nand_selected.
653 +----------------------------------------------------------------------------*/
654int is_nand_selected(void)
655{
c57c7980
SR		 656#ifdef CONFIG_BAMBOO_NAND
657 return TRUE;
658#else
659 return FALSE;
660#endif
17f50f22
SR		 661}
662
663/*----------------------------------------------------------------------------+
664 | config_on_ebc_cs4_is_small_flash => from EPLD
665 +----------------------------------------------------------------------------*/
666unsigned char config_on_ebc_cs4_is_small_flash(void)
667{
668 /* Not implemented yet => returns constant value */
669 return TRUE;
670}
671
672/*----------------------------------------------------------------------------+
673 | Ext_bus_cntlr_init.
674 | Initialize the external bus controller
675 +----------------------------------------------------------------------------*/
676void ext_bus_cntlr_init(void)
677{
678 unsigned long sdr0_pstrp0, sdr0_sdstp1;
679 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
f901a83b 680 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
17f50f22
SR		 681 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
682 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
683 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
684 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
685 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
686
687
688 /*-------------------------------------------------------------------------+
689 |
690 | PART 1 : Initialize EBC Bank 5
691 | ==============================
692 | Bank5 is always associated to the NVRAM/EPLD.
693 | It has to be initialized prior to other banks settings computation since
694 | some board registers values may be needed
695 |
696 +-------------------------------------------------------------------------*/
697 /* NVRAM - FPGA */
698 mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
699 mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
700
701 /*-------------------------------------------------------------------------+
702 |
703 | PART 2 : Determine which boot device was selected
704 | =========================================
705 |
706 | Read Pin Strap Register in PPC440EP
707 | In case of boot from IIC, read Serial Device Strap Register1
708 |
709 | Result can either be :
710 | - Boot from EBC 8bits => SMALL FLASH
711 | - Boot from EBC 16bits => Large Flash or SRAM
712 | - Boot from NAND Flash
713 | - Boot from PCI
714 |
715 +-------------------------------------------------------------------------*/
716 /* Read Pin Strap Register in PPC440EP */
717 mfsdr(sdr_pstrp0, sdr0_pstrp0);
718 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
719
720 /*-------------------------------------------------------------------------+
721 | PPC440EP Pass1
722 +-------------------------------------------------------------------------*/
723 if (is_powerpc440ep_pass1() == TRUE) {
724 switch(bootstrap_settings) {
725 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
726 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
727 /* Boot from Small Flash */
728 computed_boot_device = BOOT_FROM_SMALL_FLASH;
729 break;
730 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
731 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
732 /* Boot from PCI */
733 computed_boot_device = BOOT_FROM_PCI;
734 break;
735
736 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
737 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
738 /* Boot from Nand Flash */
739 computed_boot_device = BOOT_FROM_NAND_FLASH0;
740 break;
741
742 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
743 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
744 /* Boot from Small Flash */
745 computed_boot_device = BOOT_FROM_SMALL_FLASH;
746 break;
747
748 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
749 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
750 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
751 /* Read Serial Device Strap Register1 in PPC440EP */
752 mfsdr(sdr_sdstp1, sdr0_sdstp1);
f901a83b
WD		 753 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
754 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
17f50f22
SR		 755
756 switch(boot_selection) {
757 case SDR0_SDSTP1_BOOT_SEL_EBC:
758 switch(ebc_boot_size) {
759 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
760 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
761 break;
762 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
763 computed_boot_device = BOOT_FROM_SMALL_FLASH;
764 break;
765 }
766 break;
767
768 case SDR0_SDSTP1_BOOT_SEL_PCI:
769 computed_boot_device = BOOT_FROM_PCI;
770 break;
771
772 case SDR0_SDSTP1_BOOT_SEL_NDFC:
773 computed_boot_device = BOOT_FROM_NAND_FLASH0;
774 break;
775 }
776 break;
777 }
778 }
779
780 /*-------------------------------------------------------------------------+
781 | PPC440EP Pass2
782 +-------------------------------------------------------------------------*/
783 else {
784 switch(bootstrap_settings) {
785 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
786 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
787 /* Boot from Small Flash */
788 computed_boot_device = BOOT_FROM_SMALL_FLASH;
789 break;
790 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
791 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
792 /* Boot from PCI */
793 computed_boot_device = BOOT_FROM_PCI;
794 break;
795
796 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
797 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
798 /* Boot from Nand Flash */
799 computed_boot_device = BOOT_FROM_NAND_FLASH0;
800 break;
801
802 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
803 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
804 /* Boot from Large Flash or SRAM */
805 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
806 break;
807
808 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
809 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
810 /* Boot from Large Flash or SRAM */
811 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
812 break;
813
814 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
815 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
816 /* Boot from PCI */
817 computed_boot_device = BOOT_FROM_PCI;
818 break;
819
820 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
821 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
822 /* Default Strap Settings 5-7 */
823 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
824 /* Read Serial Device Strap Register1 in PPC440EP */
825 mfsdr(sdr_sdstp1, sdr0_sdstp1);
f901a83b
WD		 826 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
827 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
17f50f22
SR		 828
829 switch(boot_selection) {
830 case SDR0_SDSTP1_BOOT_SEL_EBC:
831 switch(ebc_boot_size) {
832 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
833 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
834 break;
835 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
836 computed_boot_device = BOOT_FROM_SMALL_FLASH;
837 break;
838 }
839 break;
840
841 case SDR0_SDSTP1_BOOT_SEL_PCI:
842 computed_boot_device = BOOT_FROM_PCI;
843 break;
844
845 case SDR0_SDSTP1_BOOT_SEL_NDFC:
846 computed_boot_device = BOOT_FROM_NAND_FLASH0;
847 break;
848 }
849 break;
850 }
851 }
852
853 /*-------------------------------------------------------------------------+
854 |
855 | PART 3 : Compute EBC settings depending on selected boot device
856 | ====== ======================================================
857 |
858 | Resulting EBC init will be among following configurations :
859 |
860 | - Boot from EBC 8bits => boot from SMALL FLASH selected
f901a83b
WD		 861 | EBC-CS0 = Small Flash
862 | EBC-CS1,2,3 = NAND Flash or
863 | Exp.Slot depending on Soft Config
864 | EBC-CS4 = SRAM/Large Flash or
865 | Large Flash/SRAM depending on jumpers
866 | EBC-CS5 = NVRAM / EPLD
17f50f22
SR		 867 |
868 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
f901a83b
WD		 869 | EBC-CS0 = SRAM/Large Flash or
870 | Large Flash/SRAM depending on jumpers
871 | EBC-CS1,2,3 = NAND Flash or
872 | Exp.Slot depending on Software Configuration
873 | EBC-CS4 = Small Flash
874 | EBC-CS5 = NVRAM / EPLD
17f50f22
SR		 875 |
876 | - Boot from NAND Flash
f901a83b
WD		 877 | EBC-CS0 = NAND Flash0
878 | EBC-CS1,2,3 = NAND Flash1
879 | EBC-CS4 = SRAM/Large Flash or
880 | Large Flash/SRAM depending on jumpers
881 | EBC-CS5 = NVRAM / EPLD
17f50f22
SR		 882 |
883 | - Boot from PCI
f901a83b
WD		 884 | EBC-CS0 = ...
885 | EBC-CS1,2,3 = NAND Flash or
886 | Exp.Slot depending on Software Configuration
887 | EBC-CS4 = SRAM/Large Flash or
888 | Large Flash/SRAM or
889 | Small Flash depending on jumpers
890 | EBC-CS5 = NVRAM / EPLD
17f50f22
SR		 891 |
892 +-------------------------------------------------------------------------*/
893
894 switch(computed_boot_device) {
895 /*------------------------------------------------------------------------- */
f901a83b 896 case BOOT_FROM_SMALL_FLASH:
17f50f22
SR		 897 /*------------------------------------------------------------------------- */
898 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
899 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
900 if ((is_nand_selected()) == TRUE) {
901 /* NAND Flash */
902 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
903 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
c57c7980
SR		 904 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
905 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
17f50f22
SR		 906 ebc0_cs3_bnap_value = 0;
907 ebc0_cs3_bncr_value = 0;
908 } else {
909 /* Expansion Slot */
910 ebc0_cs1_bnap_value = 0;
911 ebc0_cs1_bncr_value = 0;
912 ebc0_cs2_bnap_value = 0;
913 ebc0_cs2_bncr_value = 0;
914 ebc0_cs3_bnap_value = 0;
915 ebc0_cs3_bncr_value = 0;
916 }
917 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
918 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
919
920 break;
921
922 /*------------------------------------------------------------------------- */
f901a83b 923 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
17f50f22
SR		 924 /*------------------------------------------------------------------------- */
925 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
926 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
927 if ((is_nand_selected()) == TRUE) {
928 /* NAND Flash */
929 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
930 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
931 ebc0_cs2_bnap_value = 0;
932 ebc0_cs2_bncr_value = 0;
933 ebc0_cs3_bnap_value = 0;
934 ebc0_cs3_bncr_value = 0;
935 } else {
936 /* Expansion Slot */
937 ebc0_cs1_bnap_value = 0;
938 ebc0_cs1_bncr_value = 0;
939 ebc0_cs2_bnap_value = 0;
940 ebc0_cs2_bncr_value = 0;
941 ebc0_cs3_bnap_value = 0;
942 ebc0_cs3_bncr_value = 0;
943 }
944 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
945 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
946
947 break;
948
949 /*------------------------------------------------------------------------- */
f901a83b 950 case BOOT_FROM_NAND_FLASH0:
17f50f22 951 /*------------------------------------------------------------------------- */
a471db07
SR		 952 ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
953 ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
17f50f22 954
a471db07
SR		 955 ebc0_cs1_bnap_value = 0;
956 ebc0_cs1_bncr_value = 0;
17f50f22
SR		 957 ebc0_cs2_bnap_value = 0;
958 ebc0_cs2_bncr_value = 0;
959 ebc0_cs3_bnap_value = 0;
960 ebc0_cs3_bncr_value = 0;
961
962 /* Large Flash or SRAM */
963 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
964 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
965
966 break;
967
968 /*------------------------------------------------------------------------- */
f901a83b 969 case BOOT_FROM_PCI:
17f50f22
SR		 970 /*------------------------------------------------------------------------- */
971 ebc0_cs0_bnap_value = 0;
972 ebc0_cs0_bncr_value = 0;
973
974 if ((is_nand_selected()) == TRUE) {
975 /* NAND Flash */
976 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
977 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
978 ebc0_cs2_bnap_value = 0;
979 ebc0_cs2_bncr_value = 0;
980 ebc0_cs3_bnap_value = 0;
981 ebc0_cs3_bncr_value = 0;
982 } else {
983 /* Expansion Slot */
984 ebc0_cs1_bnap_value = 0;
985 ebc0_cs1_bncr_value = 0;
986 ebc0_cs2_bnap_value = 0;
987 ebc0_cs2_bncr_value = 0;
988 ebc0_cs3_bnap_value = 0;
989 ebc0_cs3_bncr_value = 0;
990 }
991
992 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
993 /* Small Flash */
994 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
995 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
996 } else {
997 /* Large Flash or SRAM */
998 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
999 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
1000 }
1001
1002 break;
1003
1004 /*------------------------------------------------------------------------- */
f901a83b 1005 case BOOT_DEVICE_UNKNOWN:
17f50f22
SR		 1006 /*------------------------------------------------------------------------- */
1007 /* Error */
1008 break;
1009
1010 }
1011
1012
1013 /*-------------------------------------------------------------------------+
1014 | Initialize EBC CONFIG
1015 +-------------------------------------------------------------------------*/
1016 mtdcr(ebccfga, xbcfg);
f901a83b
WD		 1017 mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
1018 EBC0_CFG_PTD_ENABLED |
1019 EBC0_CFG_RTC_2048PERCLK |
1020 EBC0_CFG_EMPL_LOW |
1021 EBC0_CFG_EMPH_LOW |
1022 EBC0_CFG_CSTC_DRIVEN |
1023 EBC0_CFG_BPF_ONEDW |
1024 EBC0_CFG_EMS_8BIT |
1025 EBC0_CFG_PME_DISABLED |
1026 EBC0_CFG_PMT_ENCODE(0) );
17f50f22
SR		 1027
1028 /*-------------------------------------------------------------------------+
1029 | Initialize EBC Bank 0-4
1030 +-------------------------------------------------------------------------*/
1031 /* EBC Bank0 */
1032 mtebc(pb0ap, ebc0_cs0_bnap_value);
1033 mtebc(pb0cr, ebc0_cs0_bncr_value);
1034 /* EBC Bank1 */
1035 mtebc(pb1ap, ebc0_cs1_bnap_value);
1036 mtebc(pb1cr, ebc0_cs1_bncr_value);
1037 /* EBC Bank2 */
1038 mtebc(pb2ap, ebc0_cs2_bnap_value);
1039 mtebc(pb2cr, ebc0_cs2_bncr_value);
1040 /* EBC Bank3 */
1041 mtebc(pb3ap, ebc0_cs3_bnap_value);
1042 mtebc(pb3cr, ebc0_cs3_bncr_value);
1043 /* EBC Bank4 */
1044 mtebc(pb4ap, ebc0_cs4_bnap_value);
1045 mtebc(pb4cr, ebc0_cs4_bncr_value);
1046
1047 return;
1048}
1049
1050
1051/*----------------------------------------------------------------------------+
1052 | get_uart_configuration.
1053 +----------------------------------------------------------------------------*/
1054uart_config_nb_t get_uart_configuration(void)
8a316c9b 1055{
c57c7980 1056 return (L4);
17f50f22
SR		 1057}
1058
1059/*----------------------------------------------------------------------------+
1060 | set_phy_configuration_through_fpga => to EPLD
1061 +----------------------------------------------------------------------------*/
1062void set_phy_configuration_through_fpga(zmii_config_t config)
1063{
1064
1065 unsigned long fpga_selection_reg;
1066
1067 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1068
1069 switch(config)
1070 {
f901a83b 1071 case ZMII_CONFIGURATION_IS_MII:
17f50f22
SR		 1072 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1073 break;
f901a83b 1074 case ZMII_CONFIGURATION_IS_RMII:
17f50f22
SR		 1075 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1076 break;
f901a83b 1077 case ZMII_CONFIGURATION_IS_SMII:
17f50f22
SR		 1078 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1079 break;
f901a83b
WD		 1080 case ZMII_CONFIGURATION_UNKNOWN:
1081 default:
17f50f22
SR		 1082 break;
1083 }
1084 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
8a316c9b
SR		 1085
1086}
17f50f22
SR		 1087
1088/*----------------------------------------------------------------------------+
1089 | scp_selection_in_fpga.
1090 +----------------------------------------------------------------------------*/
1091void scp_selection_in_fpga(void)
1092{
1093 unsigned long fpga_selection_2_reg;
1094
1095 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1096 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1097 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1098}
1099
1100/*----------------------------------------------------------------------------+
1101 | iic1_selection_in_fpga.
1102 +----------------------------------------------------------------------------*/
1103void iic1_selection_in_fpga(void)
1104{
1105 unsigned long fpga_selection_2_reg;
1106
1107 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1108 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1109 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1110}
1111
1112/*----------------------------------------------------------------------------+
1113 | dma_a_b_selection_in_fpga.
1114 +----------------------------------------------------------------------------*/
1115void dma_a_b_selection_in_fpga(void)
1116{
1117 unsigned long fpga_selection_2_reg;
1118
1119 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1120 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1121}
1122
1123/*----------------------------------------------------------------------------+
1124 | dma_a_b_unselect_in_fpga.
1125 +----------------------------------------------------------------------------*/
1126void dma_a_b_unselect_in_fpga(void)
1127{
1128 unsigned long fpga_selection_2_reg;
1129
1130 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1131 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1132}
1133
1134/*----------------------------------------------------------------------------+
1135 | dma_c_d_selection_in_fpga.
1136 +----------------------------------------------------------------------------*/
1137void dma_c_d_selection_in_fpga(void)
1138{
1139 unsigned long fpga_selection_2_reg;
1140
1141 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1142 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1143}
1144
1145/*----------------------------------------------------------------------------+
1146 | dma_c_d_unselect_in_fpga.
1147 +----------------------------------------------------------------------------*/
1148void dma_c_d_unselect_in_fpga(void)
1149{
1150 unsigned long fpga_selection_2_reg;
1151
1152 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1153 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1154}
1155
1156/*----------------------------------------------------------------------------+
1157 | usb2_device_selection_in_fpga.
1158 +----------------------------------------------------------------------------*/
1159void usb2_device_selection_in_fpga(void)
1160{
1161 unsigned long fpga_selection_1_reg;
1162
1163 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1164 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1165}
1166
1167/*----------------------------------------------------------------------------+
1168 | usb2_device_reset_through_fpga.
1169 +----------------------------------------------------------------------------*/
1170void usb2_device_reset_through_fpga(void)
1171{
1172 /* Perform soft Reset pulse */
1173 unsigned long fpga_reset_reg;
1174 int i;
1175
1176 fpga_reset_reg = in8(FPGA_RESET_REG);
1177 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1178 for (i=0; i<500; i++)
1179 udelay(1000);
1180 out8(FPGA_RESET_REG,fpga_reset_reg);
1181}
1182
1183/*----------------------------------------------------------------------------+
1184 | usb2_host_selection_in_fpga.
1185 +----------------------------------------------------------------------------*/
1186void usb2_host_selection_in_fpga(void)
1187{
1188 unsigned long fpga_selection_1_reg;
1189
1190 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1191 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1192}
1193
1194/*----------------------------------------------------------------------------+
1195 | ndfc_selection_in_fpga.
1196 +----------------------------------------------------------------------------*/
1197void ndfc_selection_in_fpga(void)
1198{
1199 unsigned long fpga_selection_1_reg;
1200
1201 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1202 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
c57c7980 1203 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
17f50f22
SR		 1204 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1205}
1206
1207/*----------------------------------------------------------------------------+
1208 | uart_selection_in_fpga.
1209 +----------------------------------------------------------------------------*/
1210void uart_selection_in_fpga(uart_config_nb_t uart_config)
1211{
1212 /* FPGA register */
f901a83b 1213 unsigned char fpga_selection_3_reg;
17f50f22
SR		 1214
1215 /* Read FPGA Reagister */
1216 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1217
1218 switch (uart_config)
1219 {
1220 case L1:
1221 /* ----------------------------------------------------------------------- */
f901a83b 1222 /* L1 configuration: UART0 = 8 pins */
17f50f22
SR		 1223 /* ----------------------------------------------------------------------- */
1224 /* Configure FPGA */
f901a83b
WD		 1225 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1226 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
17f50f22
SR		 1227 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1228
1229 break;
1230
1231 case L2:
1232 /* ----------------------------------------------------------------------- */
f901a83b
WD		 1233 /* L2 configuration: UART0 = 4 pins */
1234 /* UART1 = 4 pins */
17f50f22
SR		 1235 /* ----------------------------------------------------------------------- */
1236 /* Configure FPGA */
f901a83b
WD		 1237 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1238 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
17f50f22
SR		 1239 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1240
1241 break;
1242
1243 case L3:
1244 /* ----------------------------------------------------------------------- */
f901a83b
WD		 1245 /* L3 configuration: UART0 = 4 pins */
1246 /* UART1 = 2 pins */
1247 /* UART2 = 2 pins */
17f50f22
SR		 1248 /* ----------------------------------------------------------------------- */
1249 /* Configure FPGA */
f901a83b
WD		 1250 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1251 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
17f50f22
SR		 1252 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1253 break;
1254
1255 case L4:
1256 /* Configure FPGA */
f901a83b
WD		 1257 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1258 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
17f50f22
SR		 1259 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1260
1261 break;
1262
1263 default:
1264 /* Unsupported UART configuration number */
1265 for (;;)
1266 ;
1267 break;
1268
1269 }
1270}
1271
1272
1273/*----------------------------------------------------------------------------+
1274 | init_default_gpio
1275 +----------------------------------------------------------------------------*/
d2f68006 1276void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22
SR		 1277{
1278 int i;
1279
1280 /* Init GPIO0 */
1281 for(i=0; i<GPIO_MAX; i++)
1282 {
f901a83b 1283 gpio_tab[GPIO0][i].add = GPIO0_BASE;
17f50f22
SR		 1284 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1285 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1286 }
1287
1288 /* Init GPIO1 */
1289 for(i=0; i<GPIO_MAX; i++)
1290 {
f901a83b 1291 gpio_tab[GPIO1][i].add = GPIO1_BASE;
17f50f22
SR		 1292 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1293 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1294 }
1295
1296 /* EBC_CS_N(5) - GPIO0_10 */
1297 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1298 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1299
1300 /* EBC_CS_N(4) - GPIO0_9 */
1301 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1302 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1303}
1304
1305/*----------------------------------------------------------------------------+
1306 | update_uart_ios
1307 +------------------------------------------------------------------------------
1308 |
1309 | Set UART Configuration in PowerPC440EP
1310 |
1311 | +---------------------------------------------------------------------+
f901a83b
WD		 1312 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1313 | | Number | Port Name | available | naming | CORE |
17f50f22 1314 | +-----------------+---------------+------------+--------+-------------+
f901a83b 1315 | | L1 | Port_A | 8 | UART | UART core 0 |
17f50f22 1316 | +-----------------+---------------+------------+--------+-------------+
f901a83b
WD		 1317 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1318 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
17f50f22 1319 | +-----------------+---------------+------------+--------+-------------+
f901a83b
WD		 1320 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1321 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1322 | | | Port_C | 2 | UART3 | UART core 2 |
17f50f22 1323 | +-----------------+---------------+------------+--------+-------------+
f901a83b
WD		 1324 | | | Port_A | 2 | UART1 | UART core 0 |
1325 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1326 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1327 | | | Port_D | 2 | UART4 | UART core 3 |
17f50f22
SR		 1328 | +-----------------+---------------+------------+--------+-------------+
1329 |
1330 | Involved GPIOs
1331 |
1332 | +------------------------------------------------------------------------------+
f901a83b 1333 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
17f50f22 1334 | +---------+------------------+-----+-----------------+-----+-------------+-----+
f901a83b
WD		 1335 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1336 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1337 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1338 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1339 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1340 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
17f50f22
SR		 1341 | +------------------------------------------------------------------------------+
1342 |
1343 |
1344 +----------------------------------------------------------------------------*/
1345
d2f68006 1346void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22
SR		 1347{
1348 switch (uart_config)
1349 {
1350 case L1:
1351 /* ----------------------------------------------------------------------- */
f901a83b 1352 /* L1 configuration: UART0 = 8 pins */
17f50f22
SR		 1353 /* ----------------------------------------------------------------------- */
1354 /* Update GPIO Configuration Table */
1355 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1356 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1357
1358 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1359 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1360
1361 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1362 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1363
1364 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1365 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1366
1367 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1368 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1369
1370 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1371 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1372
1373 break;
1374
1375 case L2:
1376 /* ----------------------------------------------------------------------- */
f901a83b
WD		 1377 /* L2 configuration: UART0 = 4 pins */
1378 /* UART1 = 4 pins */
17f50f22
SR		 1379 /* ----------------------------------------------------------------------- */
1380 /* Update GPIO Configuration Table */
1381 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1382 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1383
1384 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1385 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1386
1387 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1388 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1389
1390 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1391 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1392
1393 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1394 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1395
1396 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1397 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1398
1399 break;
1400
1401 case L3:
1402 /* ----------------------------------------------------------------------- */
f901a83b
WD		 1403 /* L3 configuration: UART0 = 4 pins */
1404 /* UART1 = 2 pins */
1405 /* UART2 = 2 pins */
17f50f22
SR		 1406 /* ----------------------------------------------------------------------- */
1407 /* Update GPIO Configuration Table */
1408 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1409 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1410
1411 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1412 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1413
1414 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1415 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1416
1417 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1418 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1419
1420 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1421 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1422
1423 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1424 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1425
1426 break;
1427
1428 case L4:
1429 /* ----------------------------------------------------------------------- */
f901a83b
WD		 1430 /* L4 configuration: UART0 = 2 pins */
1431 /* UART1 = 2 pins */
1432 /* UART2 = 2 pins */
1433 /* UART3 = 2 pins */
17f50f22
SR		 1434 /* ----------------------------------------------------------------------- */
1435 /* Update GPIO Configuration Table */
1436 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1437 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1438
1439 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1440 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1441
1442 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1443 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1444
1445 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1446 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1447
1448 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1449 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1450
1451 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1452 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1453
1454 break;
1455
1456 default:
1457 /* Unsupported UART configuration number */
1458 printf("ERROR - Unsupported UART configuration number.\n\n");
1459 for (;;)
1460 ;
1461 break;
1462
1463 }
1464
1465 /* Set input Selection Register on Alt_Receive for UART Input Core */
1466 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1467 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1468 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1469}
1470
1471/*----------------------------------------------------------------------------+
1472 | update_ndfc_ios(void).
1473 +----------------------------------------------------------------------------*/
d2f68006 1474void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1475{
f901a83b
WD		 1476 /* Update GPIO Configuration Table */
1477 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1478 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
17f50f22 1479
f901a83b 1480 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
17f50f22
SR		 1481 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1482
a471db07 1483#if 0
f901a83b 1484 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
17f50f22 1485 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
8a316c9b 1486#endif
17f50f22
SR		 1487}
1488
1489/*----------------------------------------------------------------------------+
1490 | update_zii_ios(void).
1491 +----------------------------------------------------------------------------*/
d2f68006 1492void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1493{
f901a83b
WD		 1494 /* Update GPIO Configuration Table */
1495 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1496 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
17f50f22 1497
f901a83b
WD		 1498 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1499 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
17f50f22 1500
f901a83b
WD		 1501 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1502 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
17f50f22 1503
f901a83b
WD		 1504 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1505 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
17f50f22 1506
f901a83b
WD		 1507 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1508 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
17f50f22 1509
f901a83b
WD		 1510 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1511 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
17f50f22 1512
f901a83b
WD		 1513 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1514 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
17f50f22 1515
f901a83b
WD		 1516 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1517 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
17f50f22 1518
f901a83b
WD		 1519 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1520 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
17f50f22 1521
f901a83b
WD		 1522 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1523 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
17f50f22 1524
f901a83b
WD		 1525 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1526 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
17f50f22 1527
f901a83b
WD		 1528 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1529 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
17f50f22 1530
f901a83b
WD		 1531 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1532 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
17f50f22 1533
f901a83b
WD		 1534 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1535 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
17f50f22
SR		 1536
1537}
1538
1539/*----------------------------------------------------------------------------+
1540 | update_uic_0_3_irq_ios().
1541 +----------------------------------------------------------------------------*/
d2f68006 1542void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1543{
f901a83b 1544 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
17f50f22
SR		 1545 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1546
f901a83b 1547 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
17f50f22
SR		 1548 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1549
f901a83b 1550 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
17f50f22
SR		 1551 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1552
f901a83b 1553 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
17f50f22
SR		 1554 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1555}
1556
1557/*----------------------------------------------------------------------------+
1558 | update_uic_4_9_irq_ios().
1559 +----------------------------------------------------------------------------*/
d2f68006 1560void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1561{
f901a83b 1562 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
17f50f22
SR		 1563 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1564
f901a83b 1565 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
17f50f22
SR		 1566 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1567
f901a83b 1568 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
17f50f22
SR		 1569 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1570
f901a83b 1571 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
17f50f22
SR		 1572 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1573
f901a83b 1574 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
17f50f22
SR		 1575 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1576}
1577
1578/*----------------------------------------------------------------------------+
1579 | update_dma_a_b_ios().
1580 +----------------------------------------------------------------------------*/
d2f68006 1581void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1582{
f901a83b 1583 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
17f50f22
SR		 1584 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1585
f901a83b 1586 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
17f50f22
SR		 1587 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1588
f901a83b 1589 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
17f50f22
SR		 1590 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1591
f901a83b 1592 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
17f50f22
SR		 1593 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1594
f901a83b 1595 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
17f50f22
SR		 1596 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1597}
1598
1599/*----------------------------------------------------------------------------+
1600 | update_dma_c_d_ios().
1601 +----------------------------------------------------------------------------*/
d2f68006 1602void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1603{
f901a83b 1604 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
17f50f22
SR		 1605 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1606
f901a83b 1607 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
17f50f22
SR		 1608 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1609
f901a83b 1610 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
17f50f22
SR		 1611 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1612
f901a83b 1613 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
17f50f22
SR		 1614 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1615
f901a83b 1616 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
17f50f22
SR		 1617 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1618
f901a83b 1619 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
17f50f22
SR		 1620 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1621
1622}
1623
1624/*----------------------------------------------------------------------------+
1625 | update_ebc_master_ios().
1626 +----------------------------------------------------------------------------*/
d2f68006 1627void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1628{
f901a83b 1629 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
17f50f22
SR		 1630 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1631
f901a83b 1632 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
17f50f22
SR		 1633 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1634
f901a83b 1635 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
17f50f22
SR		 1636 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1637
f901a83b 1638 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
17f50f22
SR		 1639 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1640}
1641
1642/*----------------------------------------------------------------------------+
1643 | update_usb2_device_ios().
1644 +----------------------------------------------------------------------------*/
d2f68006 1645void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1646{
f901a83b 1647 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
17f50f22
SR		 1648 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1649
f901a83b 1650 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
17f50f22
SR		 1651 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1652
f901a83b 1653 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
17f50f22
SR		 1654 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1655
f901a83b 1656 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
17f50f22
SR		 1657 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1658
f901a83b 1659 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
17f50f22
SR		 1660 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1661
f901a83b 1662 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
17f50f22
SR		 1663 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1664
f901a83b 1665 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
17f50f22
SR		 1666 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1667
f901a83b 1668 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
17f50f22
SR		 1669 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1670
1671}
1672
1673/*----------------------------------------------------------------------------+
1674 | update_pci_patch_ios().
1675 +----------------------------------------------------------------------------*/
d2f68006 1676void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22 1677{
f901a83b 1678 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
17f50f22
SR		 1679 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1680}
1681
1682/*----------------------------------------------------------------------------+
d2f68006
EO		 1683 | set_chip_gpio_configuration(unsigned char gpio_core,
1684 | gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22
SR		 1685 | Put the core impacted by clock modification and sharing in reset.
1686 | Config the select registers to resolve the sharing depending of the config.
1687 | Configure the GPIO registers.
1688 |
1689 +----------------------------------------------------------------------------*/
d2f68006 1690void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
17f50f22
SR		 1691{
1692 unsigned char i=0, j=0, reg_offset = 0;
1693 unsigned long gpio_reg, gpio_core_add;
1694
1695 /* GPIO config of the GPIOs 0 to 31 */
1696 for (i=0; i<GPIO_MAX; i++, j++)
1697 {
1698 if (i == GPIO_MAX/2)
1699 {
1700 reg_offset = 4;
1701 j = i-16;
1702 }
1703
1704 gpio_core_add = gpio_tab[gpio_core][i].add;
1705
1706 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1707 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1708 {
1709 switch (gpio_tab[gpio_core][i].alt_nb)
1710 {
1711 case GPIO_SEL:
1712 break;
1713
1714 case GPIO_ALT1:
1715 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1716 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1717 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1718 break;
1719
1720 case GPIO_ALT2:
1721 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1722 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1723 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1724 break;
1725
1726 case GPIO_ALT3:
1727 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1728 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1729 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1730 break;
1731 }
1732 }
1733 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1734 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1735 {
1736
1737 switch (gpio_tab[gpio_core][i].alt_nb)
1738 {
1739 case GPIO_SEL:
1740 break;
1741 case GPIO_ALT1:
1742 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1743 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1744 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1745 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1746 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1747 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1748 break;
1749 case GPIO_ALT2:
1750 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1751 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1752 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1753 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1754 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1755 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1756 break;
1757 case GPIO_ALT3:
1758 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1759 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1760 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1761 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1762 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1763 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1764 break;
1765 }
1766 }
1767 }
1768}
1769
1770/*----------------------------------------------------------------------------+
1771 | force_bup_core_selection.
1772 +----------------------------------------------------------------------------*/
1773void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1774{
1775 /* Pointer invalid */
1776 if (core_select_P == NULL)
1777 {
1778 printf("Configuration invalid pointer 1\n");
1779 for (;;)
1780 ;
1781 }
1782
1783 /* L4 Selection */
f901a83b
WD		 1784 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1785 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1786 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1787 *(core_select_P+UART_CORE3) = CORE_SELECTED;
17f50f22
SR		 1788
1789 /* RMII Selection */
f901a83b 1790 *(core_select_P+RMII_SEL) = CORE_SELECTED;
17f50f22
SR		 1791
1792 /* External Interrupt 0-9 selection */
f901a83b
WD		 1793 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1794 *(core_select_P+UIC_4_9) = CORE_SELECTED;
17f50f22 1795
c57c7980
SR		 1796 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1797 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1798 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
f901a83b 1799 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
17f50f22 1800
c57c7980
SR		 1801 if (is_nand_selected()) {
1802 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1803 }
1804
17f50f22
SR		 1805 *config_val_P = CONFIG_IS_VALID;
1806
1807}
1808
1809/*----------------------------------------------------------------------------+
1810 | configure_ppc440ep_pins.
1811 +----------------------------------------------------------------------------*/
1812void configure_ppc440ep_pins(void)
1813{
1814 uart_config_nb_t uart_configuration;
1815 config_validity_t config_val = CONFIG_IS_INVALID;
1816
1817 /* Create Core Selection Table */
1818 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1819 {
f901a83b
WD		 1820 CORE_NOT_SELECTED, /* IIC_CORE, */
1821 CORE_NOT_SELECTED, /* SPC_CORE, */
1822 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1823 CORE_NOT_SELECTED, /* UIC_4_9, */
1824 CORE_NOT_SELECTED, /* USB2_HOST, */
1825 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1826 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1827 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1828 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1829 CORE_NOT_SELECTED, /* EBC_MASTER, */
1830 CORE_NOT_SELECTED, /* NAND_FLASH, */
1831 CORE_NOT_SELECTED, /* UART_CORE0, */
1832 CORE_NOT_SELECTED, /* UART_CORE1, */
1833 CORE_NOT_SELECTED, /* UART_CORE2, */
1834 CORE_NOT_SELECTED, /* UART_CORE3, */
1835 CORE_NOT_SELECTED, /* MII_SEL, */
1836 CORE_NOT_SELECTED, /* RMII_SEL, */
1837 CORE_NOT_SELECTED, /* SMII_SEL, */
1838 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1839 CORE_NOT_SELECTED, /* UIC_0_3 */
1840 CORE_NOT_SELECTED, /* USB1_HOST */
1841 CORE_NOT_SELECTED /* PCI_PATCH */
17f50f22
SR		 1842 };
1843
d2f68006 1844 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
17f50f22
SR		 1845
1846 /* Table Default Initialisation + FPGA Access */
d2f68006
EO		 1847 init_default_gpio(gpio_tab);
1848 set_chip_gpio_configuration(GPIO0, gpio_tab);
1849 set_chip_gpio_configuration(GPIO1, gpio_tab);
17f50f22
SR		 1850
1851 /* Update Table */
1852 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1853#if 0 /* test-only */
1854 /* If we are running PIBS 1, force known configuration */
1855 update_core_selection_table(ppc440ep_core_selection, &config_val);
1856#endif
1857
1858 /*----------------------------------------------------------------------------+
1859 | SDR + ios table update + fpga initialization
1860 +----------------------------------------------------------------------------*/
f901a83b
WD		 1861 unsigned long sdr0_pfc1 = 0;
1862 unsigned long sdr0_usb0 = 0;
1863 unsigned long sdr0_mfr = 0;
17f50f22
SR		 1864
1865 /* PCI Always selected */
1866
1867 /* I2C Selection */
1868 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1869 {
1870 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1871 iic1_selection_in_fpga();
1872 }
1873
1874 /* SCP Selection */
1875 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1876 {
1877 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1878 scp_selection_in_fpga();
1879 }
1880
1881 /* UIC 0:3 Selection */
1882 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1883 {
d2f68006 1884 update_uic_0_3_irq_ios(gpio_tab);
17f50f22
SR		 1885 dma_a_b_unselect_in_fpga();
1886 }
1887
1888 /* UIC 4:9 Selection */
1889 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1890 {
1891 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
d2f68006 1892 update_uic_4_9_irq_ios(gpio_tab);
17f50f22
SR		 1893 }
1894
1895 /* DMA AB Selection */
1896 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1897 {
1898 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
d2f68006 1899 update_dma_a_b_ios(gpio_tab);
17f50f22
SR		 1900 dma_a_b_selection_in_fpga();
1901 }
1902
1903 /* DMA CD Selection */
1904 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1905 {
d2f68006 1906 update_dma_c_d_ios(gpio_tab);
17f50f22
SR		 1907 dma_c_d_selection_in_fpga();
1908 }
1909
1910 /* EBC Master Selection */
1911 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1912 {
1913 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1914 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
d2f68006 1915 update_ebc_master_ios(gpio_tab);
17f50f22
SR		 1916 }
1917
1918 /* PCI Patch Enable */
1919 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1920 {
1921 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
d2f68006 1922 update_pci_patch_ios(gpio_tab);
17f50f22
SR		 1923 }
1924
1925 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1926 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1927 {
1928 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1929 printf("Invalid configuration => USB2 Host selected\n");
1930 for (;;)
1931 ;
1932 /*usb2_host_selection_in_fpga(); */
1933 }
1934
1935 /* USB2.0 Device Selection */
1936 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1937 {
d2f68006 1938 update_usb2_device_ios(gpio_tab);
17f50f22
SR		 1939 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1940 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1941
1942 mfsdr(sdr_usb0, sdr0_usb0);
1943 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1944 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1945 mtsdr(sdr_usb0, sdr0_usb0);
1946
1947 usb2_device_selection_in_fpga();
1948 }
1949
1950 /* USB1.1 Device Selection */
1951 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1952 {
1953 mfsdr(sdr_usb0, sdr0_usb0);
1954 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1955 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1956 mtsdr(sdr_usb0, sdr0_usb0);
1957 }
1958
1959 /* USB1.1 Host Selection */
1960 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1961 {
1962 mfsdr(sdr_usb0, sdr0_usb0);
1963 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1964 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1965 mtsdr(sdr_usb0, sdr0_usb0);
1966 }
1967
1968 /* NAND Flash Selection */
1969 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1970 {
d2f68006 1971 update_ndfc_ios(gpio_tab);
17f50f22 1972
a471db07 1973#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
17f50f22 1974 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
f901a83b
WD		 1975 SDR0_CUST0_NDFC_ENABLE |
1976 SDR0_CUST0_NDFC_BW_8_BIT |
1977 SDR0_CUST0_NDFC_ARE_MASK |
c57c7980
SR		 1978 SDR0_CUST0_CHIPSELGAT_EN1 |
1979 SDR0_CUST0_CHIPSELGAT_EN2);
a471db07
SR		 1980#else
1981 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
1982 SDR0_CUST0_NDFC_ENABLE |
1983 SDR0_CUST0_NDFC_BW_8_BIT |
1984 SDR0_CUST0_NDFC_ARE_MASK |
1985 SDR0_CUST0_CHIPSELGAT_EN0 |
1986 SDR0_CUST0_CHIPSELGAT_EN2);
1987#endif
17f50f22
SR		 1988
1989 ndfc_selection_in_fpga();
1990 }
1991 else
1992 {
1993 /* Set Mux on EMAC */
1994 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
1995 }
1996
1997 /* MII Selection */
1998 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1999 {
d2f68006 2000 update_zii_ios(gpio_tab);
17f50f22
SR		 2001 mfsdr(sdr_mfr, sdr0_mfr);
2002 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
2003 mtsdr(sdr_mfr, sdr0_mfr);
2004
2005 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
2006 }
2007
2008 /* RMII Selection */
2009 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
2010 {
d2f68006 2011 update_zii_ios(gpio_tab);
17f50f22
SR		 2012 mfsdr(sdr_mfr, sdr0_mfr);
2013 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
2014 mtsdr(sdr_mfr, sdr0_mfr);
2015
2016 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
2017 }
2018
2019 /* SMII Selection */
2020 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
2021 {
d2f68006 2022 update_zii_ios(gpio_tab);
17f50f22
SR		 2023 mfsdr(sdr_mfr, sdr0_mfr);
2024 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
2025 mtsdr(sdr_mfr, sdr0_mfr);
2026
2027 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
2028 }
2029
2030 /* UART Selection */
2031 uart_configuration = get_uart_configuration();
2032 switch (uart_configuration)
2033 {
f901a83b 2034 case L1: /* L1 Selection */
17f50f22
SR		 2035 /* UART0 8 pins Only */
2036 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
f901a83b 2037 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
17f50f22
SR		 2038 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
2039 break;
f901a83b 2040 case L2: /* L2 Selection */
17f50f22
SR		 2041 /* UART0 and UART1 4 pins */
2042 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2043 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2044 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2045 break;
f901a83b 2046 case L3: /* L3 Selection */
17f50f22
SR		 2047 /* UART0 4 pins, UART1 and UART2 2 pins */
2048 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2049 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2050 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2051 break;
f901a83b 2052 case L4: /* L4 Selection */
17f50f22
SR		 2053 /* UART0, UART1, UART2 and UART3 2 pins */
2054 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
2055 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2056 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2057 break;
2058 }
d2f68006 2059 update_uart_ios(uart_configuration, gpio_tab);
17f50f22
SR		 2060
2061 /* UART Selection in all cases */
2062 uart_selection_in_fpga(uart_configuration);
2063
2064 /* Packet Reject Function Available */
2065 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
2066 {
2067 /* Set UPR Bit in SDR0_PFC1 Register */
2068 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
2069 }
2070
2071 /* Packet Reject Function Enable */
2072 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
2073 {
2074 mfsdr(sdr_mfr, sdr0_mfr);
2075 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
2076 mtsdr(sdr_mfr, sdr0_mfr);
2077 }
2078
2079 /* Perform effective access to hardware */
2080 mtsdr(sdr_pfc1, sdr0_pfc1);
d2f68006
EO		 2081 set_chip_gpio_configuration(GPIO0, gpio_tab);
2082 set_chip_gpio_configuration(GPIO1, gpio_tab);
17f50f22
SR		 2083
2084 /* USB2.0 Device Reset must be done after GPIO setting */
2085 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2086 usb2_device_reset_through_fpga();
2087
2088}
"Das U-Boot" Source Tree