]>
Commit | Line | Data |
---|---|---|
17f50f22 SR |
1 | /* |
2 | * (C) Copyright 2004-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> | |
6 | * Add support for Am29F016D and dynamic switch setting. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
17f50f22 SR |
9 | */ |
10 | ||
11 | /* | |
12 | * Modified 4/5/2001 | |
13 | * Wait for completion of each sector erase command issued | |
14 | * 4/5/2001 | |
15 | * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com | |
16 | */ | |
17 | ||
18 | #include <common.h> | |
b36df561 | 19 | #include <asm/ppc4xx.h> |
17f50f22 | 20 | #include <asm/processor.h> |
b36df561 | 21 | #include <asm/ppc440.h> |
17f50f22 SR |
22 | #include "bamboo.h" |
23 | ||
24 | #undef DEBUG | |
25 | ||
26 | #ifdef DEBUG | |
27 | #define DEBUGF(x...) printf(x) | |
28 | #else | |
29 | #define DEBUGF(x...) | |
30 | #endif /* DEBUG */ | |
31 | ||
6d0f6bcf | 32 | flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
17f50f22 SR |
33 | |
34 | /* | |
35 | * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 | |
36 | */ | |
6d0f6bcf | 37 | static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { |
17f50f22 SR |
38 | {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ |
39 | {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ | |
a471db07 | 40 | {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */ |
c57c7980 SR |
41 | {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/ |
42 | {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/ | |
17f50f22 SR |
43 | {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ |
44 | {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */ | |
45 | {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */ | |
c57c7980 | 46 | {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ |
17f50f22 SR |
47 | }; |
48 | ||
49 | /* | |
50 | * include common flash code (for amcc boards) | |
51 | */ | |
52 | #include "../common/flash.c" | |
53 | ||
54 | /*----------------------------------------------------------------------- | |
55 | * Functions | |
56 | */ | |
57 | static ulong flash_get_size(vu_long * addr, flash_info_t * info); | |
58 | static int write_word(flash_info_t * info, ulong dest, ulong data); | |
59 | ||
60 | /*----------------------------------------------------------------------- | |
61 | */ | |
62 | ||
63 | unsigned long flash_init(void) | |
64 | { | |
65 | unsigned long total_b = 0; | |
6d0f6bcf | 66 | unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; |
17f50f22 SR |
67 | unsigned short index = 0; |
68 | int i; | |
69 | unsigned long val; | |
70 | unsigned long ebc_boot_size; | |
71 | unsigned long boot_selection; | |
72 | ||
5e7abce9 | 73 | mfsdr(SDR0_PINSTP, val); |
17f50f22 SR |
74 | index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29; |
75 | ||
76 | if ((index == 5) || (index == 7)) { | |
77 | /* | |
78 | * Boot Settings in IIC EEprom address 0xA8 or 0xA4 | |
79 | * Read Serial Device Strap Register1 in PPC440EP | |
80 | */ | |
d1c3b275 | 81 | mfsdr(SDR0_SDSTP1, val); |
17f50f22 SR |
82 | boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; |
83 | ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; | |
84 | ||
85 | switch(boot_selection) { | |
86 | case SDR0_SDSTP1_BOOT_SEL_EBC: | |
87 | switch(ebc_boot_size) { | |
88 | case SDR0_SDSTP1_EBC_ROM_BS_16BIT: | |
89 | index = 3; | |
90 | break; | |
91 | case SDR0_SDSTP1_EBC_ROM_BS_8BIT: | |
92 | index = 0; | |
93 | break; | |
94 | } | |
95 | break; | |
96 | ||
97 | case SDR0_SDSTP1_BOOT_SEL_PCI: | |
98 | index = 1; | |
99 | break; | |
100 | ||
101 | case SDR0_SDSTP1_BOOT_SEL_NDFC: | |
102 | index = 2; | |
103 | break; | |
104 | } | |
c57c7980 SR |
105 | } else if (index == 0) { |
106 | if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) { | |
107 | index = 8; /* sram below op code flash -> new index 8 */ | |
108 | } | |
17f50f22 SR |
109 | } |
110 | ||
111 | DEBUGF("\n"); | |
112 | DEBUGF("FLASH: Index: %d\n", index); | |
113 | ||
114 | /* Init: no FLASHes known */ | |
6d0f6bcf | 115 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
17f50f22 SR |
116 | flash_info[i].flash_id = FLASH_UNKNOWN; |
117 | flash_info[i].sector_count = -1; | |
118 | flash_info[i].size = 0; | |
119 | ||
120 | /* check whether the address is 0 */ | |
a471db07 | 121 | if (flash_addr_table[index][i] == 0) |
17f50f22 | 122 | continue; |
17f50f22 | 123 | |
a471db07 | 124 | DEBUGF("Detection bank %d...\n", i); |
17f50f22 SR |
125 | /* call flash_get_size() to initialize sector address */ |
126 | size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], | |
127 | &flash_info[i]); | |
128 | flash_info[i].size = size_b[i]; | |
129 | if (flash_info[i].flash_id == FLASH_UNKNOWN) { | |
130 | printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", | |
131 | i, size_b[i], size_b[i] << 20); | |
132 | flash_info[i].sector_count = -1; | |
133 | flash_info[i].size = 0; | |
134 | } | |
135 | ||
136 | /* Monitor protection ON by default */ | |
6d0f6bcf JCPV |
137 | (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, |
138 | CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, | |
17f50f22 | 139 | &flash_info[i]); |
5a1aceb0 | 140 | #if defined(CONFIG_ENV_IS_IN_FLASH) |
0e8d1586 JCPV |
141 | (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, |
142 | CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, | |
17f50f22 | 143 | &flash_info[i]); |
0e8d1586 JCPV |
144 | #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND) |
145 | (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, | |
146 | CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, | |
17f50f22 SR |
147 | &flash_info[i]); |
148 | #endif | |
149 | #endif | |
150 | ||
151 | total_b += flash_info[i].size; | |
152 | } | |
153 | ||
154 | return total_b; | |
155 | } |