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c609719b | 1 | /* |
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2 | * (C) Copyright 2007 |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
a471db07 | 8 | */ |
c609719b | 9 | |
25ddd1fb | 10 | #include <asm-offsets.h> |
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11 | #include <ppc_asm.tmpl> |
12 | #include <config.h> | |
61f2b38a | 13 | #include <asm/mmu.h> |
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14 | |
15 | /************************************************************************** | |
16 | * TLB TABLE | |
17 | * | |
18 | * This table is used by the cpu boot code to setup the initial tlb | |
19 | * entries. Rather than make broad assumptions in the cpu source tree, | |
20 | * this table lets each board set things up however they like. | |
21 | * | |
22 | * Pointer to the table is returned in r1 | |
23 | * | |
24 | *************************************************************************/ | |
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25 | .section .bootpg,"ax" |
26 | .globl tlbtab | |
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27 | |
28 | tlbtab: | |
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29 | tlbtab_start |
30 | ||
31 | /* | |
32 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
33 | * speed up boot process. It is patched after relocation to enable SA_I | |
34 | */ | |
cf6eb6da | 35 | tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G) |
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36 | |
37 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ | |
cf6eb6da | 38 | tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) |
a471db07 | 39 | |
a471db07 | 40 | /* PCI base & peripherals */ |
cf6eb6da | 41 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG) |
a471db07 | 42 | |
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43 | tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I) |
44 | tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I) | |
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45 | |
46 | /* PCI */ | |
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47 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG) |
48 | tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG) | |
49 | tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG) | |
50 | tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG) | |
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51 | |
52 | /* USB 2.0 Device */ | |
cf6eb6da | 53 | tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG) |
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54 | |
55 | tlbtab_end |