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6e7fb6ea | 1 | /* |
00cdb4ce SR |
2 | * (C) Copyright 2007 |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
6e7fb6ea SR |
25 | |
26 | #include <ppc_asm.tmpl> | |
27 | #include <config.h> | |
61f2b38a | 28 | #include <asm/mmu.h> |
550650dd | 29 | #include <asm/ppc4xx.h> |
6e7fb6ea SR |
30 | |
31 | /************************************************************************** | |
32 | * TLB TABLE | |
33 | * | |
34 | * This table is used by the cpu boot code to setup the initial tlb | |
35 | * entries. Rather than make broad assumptions in the cpu source tree, | |
36 | * this table lets each board set things up however they like. | |
37 | * | |
38 | * Pointer to the table is returned in r1 | |
39 | * | |
40 | *************************************************************************/ | |
41 | ||
00cdb4ce SR |
42 | .section .bootpg,"ax" |
43 | .globl tlbtab | |
6e7fb6ea SR |
44 | |
45 | tlbtab: | |
00cdb4ce SR |
46 | tlbtab_start |
47 | ||
48 | /* | |
49 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
50 | * speed up boot process. It is patched after relocation to enable SA_I | |
51 | */ | |
cf6eb6da | 52 | tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G) |
00cdb4ce | 53 | |
cf6eb6da SR |
54 | tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG) |
55 | tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG) | |
56 | tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG) | |
57 | tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG) | |
58 | tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG) | |
00cdb4ce SR |
59 | |
60 | /* | |
61 | * TLB entries for SDRAM are not needed on this platform. | |
62 | * They are dynamically generated in the SPD DDR(2) detection | |
63 | * routine. | |
64 | */ | |
65 | ||
66 | /* internal ram (l2 cache) */ | |
cf6eb6da | 67 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I) |
00cdb4ce SR |
68 | |
69 | /* peripherals at f0000000 */ | |
cf6eb6da | 70 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG) |
00cdb4ce SR |
71 | |
72 | /* PCI */ | |
cf6eb6da SR |
73 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG) |
74 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG) | |
00cdb4ce | 75 | tlbtab_end |