]>
Commit | Line | Data |
---|---|---|
6e7fb6ea SR |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * John Otken, jotken@softadvances.com | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
6e7fb6ea SR |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <command.h> | |
b36df561 | 10 | #include <asm/ppc4xx.h> |
6e7fb6ea | 11 | #include <asm/processor.h> |
b14ca4b6 | 12 | #include <asm/ppc4xx-isram.h> |
6e7fb6ea SR |
13 | #include <spd_sdram.h> |
14 | #include "epld.h" | |
15 | ||
d87080b7 | 16 | DECLARE_GLOBAL_DATA_PTR; |
6e7fb6ea | 17 | |
6d0f6bcf | 18 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
6e7fb6ea SR |
19 | |
20 | ||
21 | /************************************************************************* | |
22 | * int board_early_init_f() | |
23 | * | |
24 | ************************************************************************/ | |
25 | int board_early_init_f(void) | |
26 | { | |
a27044b1 SR |
27 | u32 mfr; |
28 | ||
d1c3b275 SR |
29 | mtebc( PB0AP, 0x03800000 ); /* set chip selects */ |
30 | mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ | |
31 | mtebc( PB1AP, 0x03800000 ); | |
32 | mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ | |
33 | mtebc( PB2AP, 0x03800000 ); | |
34 | mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ | |
6e7fb6ea | 35 | |
952e7760 SR |
36 | mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */ |
37 | mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */ | |
38 | mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */ | |
39 | mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */ | |
40 | mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */ | |
41 | mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ | |
42 | mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */ | |
43 | mtdcr( UIC1SR, 0xffffffff ); | |
6e7fb6ea | 44 | |
952e7760 SR |
45 | mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */ |
46 | mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */ | |
47 | mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */ | |
48 | mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */ | |
49 | mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */ | |
50 | mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ | |
51 | mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */ | |
52 | mtdcr( UIC0SR, 0xffffffff ); | |
6e7fb6ea | 53 | |
d1c3b275 | 54 | mfsdr(SDR0_MFR, mfr); |
a27044b1 | 55 | mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ |
d1c3b275 | 56 | mtsdr(SDR0_MFR, mfr); |
a27044b1 | 57 | |
6e7fb6ea SR |
58 | return 0; |
59 | } | |
60 | ||
61 | ||
62 | /************************************************************************* | |
63 | * int misc_init_r() | |
64 | * | |
65 | ************************************************************************/ | |
66 | int misc_init_r(void) | |
67 | { | |
6d0f6bcf | 68 | volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE; |
2db64784 GB |
69 | |
70 | /* set modes of operation */ | |
71 | x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | | |
72 | EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; | |
73 | /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ | |
74 | x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; | |
738815c0 | 75 | |
2db64784 GB |
76 | /* put Ethernet+PHY in reset */ |
77 | x->ethuart &= ~EPLD2_RESET_ETH_N; | |
78 | udelay(10000); | |
79 | /* take Ethernet+PHY out of reset */ | |
80 | x->ethuart |= EPLD2_RESET_ETH_N; | |
6e7fb6ea SR |
81 | |
82 | return 0; | |
83 | } | |
84 | ||
85 | ||
86 | /************************************************************************* | |
87 | * int checkboard() | |
88 | * | |
89 | ************************************************************************/ | |
90 | int checkboard(void) | |
91 | { | |
f0c0b3a9 WD |
92 | char buf[64]; |
93 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
6e7fb6ea SR |
94 | |
95 | printf("Board: Luan - AMCC PPC440SP Evaluation Board"); | |
96 | ||
f0c0b3a9 | 97 | if (i > 0) { |
6e7fb6ea | 98 | puts(", serial# "); |
f0c0b3a9 | 99 | puts(buf); |
6e7fb6ea SR |
100 | } |
101 | putc('\n'); | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
2a49fc17 | 106 | /* |
a47a12be | 107 | * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with |
2a49fc17 SR |
108 | * board specific values. |
109 | */ | |
110 | u32 ddr_clktr(u32 default_val) { | |
111 | return (SDRAM_CLKTR_CLKP_180_DEG_ADV); | |
112 | } | |
6e7fb6ea | 113 | |
6e7fb6ea SR |
114 | /************************************************************************* |
115 | * hw_watchdog_reset | |
116 | * | |
117 | * This routine is called to reset (keep alive) the watchdog timer | |
118 | * | |
119 | ************************************************************************/ | |
120 | #if defined(CONFIG_HW_WATCHDOG) | |
121 | void hw_watchdog_reset(void) | |
122 | { | |
123 | } | |
124 | #endif | |
125 | ||
126 | ||
127 | /************************************************************************* | |
128 | * int on_off() | |
129 | * | |
130 | ************************************************************************/ | |
131 | static int on_off( const char *s ) | |
132 | { | |
133 | if (strcmp(s, "on") == 0) { | |
134 | return 1; | |
135 | } else if (strcmp(s, "off") == 0) { | |
136 | return 0; | |
137 | } | |
138 | return -1; | |
139 | } | |
140 | ||
141 | ||
142 | /************************************************************************* | |
143 | * void l2cache_disable() | |
144 | * | |
145 | ************************************************************************/ | |
146 | static void l2cache_disable(void) | |
147 | { | |
b14ca4b6 | 148 | mtdcr( L2_CACHE_CFG, 0 ); |
6e7fb6ea SR |
149 | } |
150 | ||
151 | ||
152 | /************************************************************************* | |
153 | * void l2cache_enable() | |
154 | * | |
155 | ************************************************************************/ | |
156 | static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ | |
157 | { | |
b14ca4b6 | 158 | mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ |
6e7fb6ea | 159 | |
b14ca4b6 | 160 | mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */ |
6e7fb6ea | 161 | |
b14ca4b6 | 162 | mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ |
6e7fb6ea | 163 | |
51855e89 | 164 | while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ; /* poll L2_SR for completion */ |
6e7fb6ea | 165 | |
b14ca4b6 | 166 | mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ |
6e7fb6ea | 167 | |
b14ca4b6 | 168 | mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ |
6e7fb6ea | 169 | |
b14ca4b6 DM |
170 | mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */ |
171 | mtdcr( L2_CACHE_SNP1, 0 ); | |
6e7fb6ea SR |
172 | |
173 | __asm__ volatile ("sync"); /* msync */ | |
174 | ||
b14ca4b6 | 175 | mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */ |
6e7fb6ea SR |
176 | |
177 | __asm__ volatile ("sync"); | |
178 | } | |
179 | ||
180 | ||
181 | /************************************************************************* | |
182 | * int l2cache_status() | |
183 | * | |
184 | ************************************************************************/ | |
185 | static int l2cache_status(void) | |
186 | { | |
b14ca4b6 | 187 | return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0; |
6e7fb6ea SR |
188 | } |
189 | ||
190 | ||
191 | /************************************************************************* | |
192 | * int do_l2cache() | |
193 | * | |
194 | ************************************************************************/ | |
54841ab5 | 195 | int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] ) |
6e7fb6ea SR |
196 | { |
197 | switch (argc) { | |
198 | case 2: /* on / off */ | |
199 | switch (on_off(argv[1])) { | |
200 | case 0: l2cache_disable(); | |
201 | break; | |
202 | case 1: l2cache_enable(); | |
203 | break; | |
204 | } | |
205 | /* FALL TROUGH */ | |
206 | case 1: /* get status */ | |
207 | printf ("L2 Cache is %s\n", | |
208 | l2cache_status() ? "ON" : "OFF"); | |
209 | return 0; | |
210 | default: | |
47e26b1b | 211 | return cmd_usage(cmdtp); |
6e7fb6ea SR |
212 | } |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | ||
218 | U_BOOT_CMD( | |
219 | l2cache, 2, 1, do_l2cache, | |
2fb2604d | 220 | "enable or disable L2 cache", |
6e7fb6ea | 221 | "[on, off]\n" |
a89c33db WD |
222 | " - enable or disable L2 cache" |
223 | ); |