projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0e6d798c | 1 | /* |
| 56fb6ba1 SR |
2 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 3 | * | |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 56fb6ba1 | 5 | */ |
| 0e6d798c WD |
6 | |
| 7 | #include <ppc_asm.tmpl> | |
| 8 | #include <config.h> | |
| 61f2b38a | 9 | #include <asm/mmu.h> |
| 550650dd | 10 | #include <asm/ppc4xx.h> |
| 0e6d798c WD |
11 | |
| 12 | /************************************************************************** | |
| 13 | * TLB TABLE | |
| 14 | * | |
| 15 | * This table is used by the cpu boot code to setup the initial tlb | |
| 16 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 17 | * this table lets each board set things up however they like. | |
| 18 | * | |
| 19 | * Pointer to the table is returned in r1 | |
| 20 | * | |
| 21 | *************************************************************************/ | |
| 22 | ||
| fa1aef15 SR |
23 | .section .bootpg,"ax" |
| 24 | .globl tlbtab | |
| 0e6d798c WD |
25 | |
| 26 | tlbtab: | |
| fa1aef15 SR |
27 | tlbtab_start |
| 28 | ||
| cf6eb6da | 29 | tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) |
| fa1aef15 SR |
30 | |
| 31 | /* | |
| 32 | * TLB entries for SDRAM are not needed on this platform. | |
| 33 | * They are dynamically generated in the SPD DDR(2) detection | |
| 34 | * routine. | |
| 35 | */ | |
| 36 | ||
| cf6eb6da SR |
37 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) |
| 38 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) | |
| 39 | tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) | |
| 40 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) | |
| 41 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) | |
| fa1aef15 | 42 | tlbtab_end |