projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0ce5c867 FK |
1 | /* |
| 2 | * (C) Copyright 2008 | |
| 3 | * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. | |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 0ce5c867 FK |
6 | */ |
| 7 | ||
| 8 | #include <ppc_asm.tmpl> | |
| 9 | #include <config.h> | |
| 61f2b38a | 10 | #include <asm/mmu.h> |
| 550650dd | 11 | #include <asm/ppc4xx.h> |
| 0ce5c867 FK |
12 | |
| 13 | /************************************************************************** | |
| 14 | * TLB TABLE | |
| 15 | * | |
| 16 | * This table is used by the cpu boot code to setup the initial tlb | |
| 17 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 18 | * this table lets each board set things up however they like. | |
| 19 | * | |
| 20 | * Pointer to the table is returned in r1 | |
| 21 | * | |
| 22 | *************************************************************************/ | |
| 23 | ||
| 24 | .section .bootpg,"ax" | |
| 25 | .globl tlbtab | |
| 26 | tlbtab: | |
| 27 | tlbtab_start | |
| 28 | ||
| 29 | /* | |
| 30 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
| 31 | * speed up boot process. It is patched after relocation to enable SA_I | |
| 32 | */ | |
| cf6eb6da | 33 | tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) |
| 0ce5c867 FK |
34 | |
| 35 | /* | |
| 36 | * TLB entries for SDRAM are not needed on this platform. | |
| 37 | * They are dynamically generated in the SPD DDR(2) detection | |
| 38 | * routine. | |
| 39 | */ | |
| 40 | ||
| 41 | /* Although 512 KB, map 256k at a time */ | |
| cf6eb6da SR |
42 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) |
| 43 | tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I) | |
| 0ce5c867 | 44 | |
| cf6eb6da | 45 | tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG) |
| 0ce5c867 FK |
46 | |
| 47 | /* | |
| 48 | * Peripheral base | |
| 49 | */ | |
| cf6eb6da | 50 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG) |
| 0ce5c867 | 51 | |
| cf6eb6da SR |
52 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG) |
| 53 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG) | |
| 54 | tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG) | |
| 0ce5c867 | 55 | |
| cf6eb6da SR |
56 | tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG) |
| 57 | tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG) | |
| 0ce5c867 | 58 | |
| cf6eb6da SR |
59 | tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG) |
| 60 | tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG) | |
| 61 | tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG) | |
| 0ce5c867 | 62 | tlbtab_end |