[people/ms/u-boot.git] / board / amcc / sequoia / init.S

/*
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <ppc_asm.tmpl>
#include <asm-ppc/mmu.h>
#include <config.h>

/*
 * TLB TABLE
 *
 * This table is used by the cpu boot code to setup the initial tlb
 * entries. Rather than make broad assumptions in the cpu source tree,
 * this table lets each board set things up however they like.
 *
 *  Pointer to the table is returned in r1
 */
    .section .bootpg,"ax"
    .globl tlbtab

tlbtab:
	tlbtab_start

	/* vxWorks needs this as first entry for the Machine Check interrupt */
	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )

	/*
	 * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
	 * entry is already configured for SDRAM via the JTAG debugger and mustn't
	 * be re-initialized by this RAM-booting U-Boot version.
	 */
#ifndef CONFIG_SYS_RAMBOOT
	/* TLB-entry for DDR SDRAM (Up to 2GB) */
#ifdef CONFIG_4xx_DCACHE
	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
#else
	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
#endif
#endif /* CONFIG_SYS_RAMBOOT */

	/* TLB-entry for EBC */
	tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )

	/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
	 * speed up boot process. It is patched after relocation to enable SA_I
	 */
#ifndef CONFIG_NAND_SPL
	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
#else
	tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
#endif

#ifdef CONFIG_SYS_INIT_RAM_DCACHE
	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
#endif

	/* TLB-entry for PCI Memory */
	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )

	/* TLB-entry for NAND */
	tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )

	/* TLB-entry for Internal Registers & OCM */
	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )

	/*TLB-entry PCI registers*/
	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I )

	/* TLB-entry for peripherals */
	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)

	/* TLB-entry PCI IO Space - from sr@denx.de */
	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)

	tlbtab_end

#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	/*
	 * For NAND booting the first TLB has to be reconfigured to full size
	 * and with caching disabled after running from RAM!
	 */
#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
#define TLB02	TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)

	.globl	reconfig_tlb0
reconfig_tlb0:
	sync
	isync
	addi	r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
	lis	r5,TLB00@h
	ori	r5,r5,TLB00@l
	tlbwe	r5,r4,0x0000		/* Save it out */
	lis	r5,TLB01@h
	ori	r5,r5,TLB01@l
	tlbwe	r5,r4,0x0001		/* Save it out */
	lis	r5,TLB02@h
	ori	r5,r5,TLB02@l
	tlbwe	r5,r4,0x0002		/* Save it out */
	sync
	isync
	blr
#endif
Commit	Line	Data
887e2ec9	1	/*
83a49c8d MF	2	* (C) Copyright 2008
83a49c8d MF	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
887e2ec9 SR	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <ppc_asm.tmpl>
c68f59fe	25	#include <asm-ppc/mmu.h>
887e2ec9 SR	26	#include <config.h>
887e2ec9 SR	27
83a49c8d	28	/*
887e2ec9 SR	29	* TLB TABLE
	30	*
	31	* This table is used by the cpu boot code to setup the initial tlb
	32	* entries. Rather than make broad assumptions in the cpu source tree,
	33	* this table lets each board set things up however they like.
	34	*
	35	* Pointer to the table is returned in r1
83a49c8d	36	*/
887e2ec9 SR	37	.section .bootpg,"ax"
	38	.globl tlbtab
	39
	40	tlbtab:
	41	tlbtab_start
	42
4d332dbe NG	43	/* vxWorks needs this as first entry for the Machine Check interrupt */
4d332dbe NG	44	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R\|AC_W\|AC_X\|SA_G\|SA_I )
887e2ec9	45
d873133f SR	46	/*
	47	* The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
	48	* entry is already configured for SDRAM via the JTAG debugger and mustn't
	49	* be re-initialized by this RAM-booting U-Boot version.
	50	*/
	51	#ifndef CONFIG_SYS_RAMBOOT
887e2ec9	52	/* TLB-entry for DDR SDRAM (Up to 2GB) */
ea2e1428	53	#ifdef CONFIG_4xx_DCACHE
6d0f6bcf	54	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R\|AC_W\|AC_X\|SA_G)
ea2e1428	55	#else
6d0f6bcf	56	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R\|AC_W\|AC_X\|SA_G\|SA_I )
ea2e1428	57	#endif
d873133f	58	#endif /* CONFIG_SYS_RAMBOOT */
887e2ec9	59
4d332dbe	60	/* TLB-entry for EBC */
6d0f6bcf	61	tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R\|AC_W\|AC_X\|SA_G\|SA_I )
4d332dbe NG	62
	63	/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
	64	* speed up boot process. It is patched after relocation to enable SA_I
	65	*/
	66	#ifndef CONFIG_NAND_SPL
6d0f6bcf	67	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R\|AC_W\|AC_X\|SA_G )
4d332dbe	68	#else
6d0f6bcf	69	tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R\|AC_W\|AC_X\|SA_G )
4d332dbe NG	70	#endif
4d332dbe NG	71
6d0f6bcf	72	#ifdef CONFIG_SYS_INIT_RAM_DCACHE
887e2ec9	73	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
6d0f6bcf	74	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R\|AC_W\|AC_X\|SA_G )
887e2ec9 SR	75	#endif
	76
	77	/* TLB-entry for PCI Memory */
6d0f6bcf JCPV	78	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R\|AC_W\|SA_G\|SA_I )
	79	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R\|AC_W\|SA_G\|SA_I )
	80	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R\|AC_W\|SA_G\|SA_I )
	81	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R\|AC_W\|SA_G\|SA_I )
887e2ec9	82
887e2ec9	83	/* TLB-entry for NAND */
6d0f6bcf	84	tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R\|AC_W\|AC_X\|SA_G\|SA_I )
887e2ec9 SR	85
	86	/* TLB-entry for Internal Registers & OCM */
	87	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R\|AC_W\|AC_X\|SA_I )
	88
	89	/TLB-entry PCI registers/
	90	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R\|AC_W\|AC_X\|SA_G\|SA_I )
	91
	92	/* TLB-entry for peripherals */
	93	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R\|AC_W\|AC_X\|SA_G\|SA_I)
	94
81b73dec GJ	95	/* TLB-entry PCI IO Space - from sr@denx.de */
	96	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R\|AC_W\|AC_X\|SA_G\|SA_I)
	97
887e2ec9 SR	98	tlbtab_end
	99
	100	#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	101	/*
	102	* For NAND booting the first TLB has to be reconfigured to full size
	103	* and with caching disabled after running from RAM!
	104	*/
6d0f6bcf JCPV	105	#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
6d0f6bcf JCPV	106	#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
887e2ec9 SR	107	#define TLB02 TLB2(AC_R\|AC_W\|AC_X\|SA_G\|SA_I)
	108
	109	.globl reconfig_tlb0
	110	reconfig_tlb0:
	111	sync
	112	isync
3edf68c4	113	addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
887e2ec9 SR	114	lis r5,TLB00@h
	115	ori r5,r5,TLB00@l
	116	tlbwe r5,r4,0x0000 /* Save it out */
	117	lis r5,TLB01@h
	118	ori r5,r5,TLB01@l
	119	tlbwe r5,r4,0x0001 /* Save it out */
	120	lis r5,TLB02@h
	121	ori r5,r5,TLB02@l
	122	tlbwe r5,r4,0x0002 /* Save it out */
	123	sync
	124	isync
	125	blr
	126	#endif