[people/ms/u-boot.git] / board / amcc / taishan / taishan.c

/*
 *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
 *
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>
#include <netdev.h>

#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
void show_reset_reg(void);
#endif

DECLARE_GLOBAL_DATA_PTR;

int lcd_init(void);

int board_early_init_f (void)
{
	unsigned long reg;
	volatile unsigned int *GpioOdr;
	volatile unsigned int *GpioTcr;
	volatile unsigned int *GpioOr;

	/*-------------------------------------------------------------------------+
	  | Initialize EBC CONFIG
	  +-------------------------------------------------------------------------*/
	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);

	/*-------------------------------------------------------------------------+
	  | 64MB FLASH. Initialize bank 0 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);

	/*-------------------------------------------------------------------------+
	  | FPGA. Initialize bank 1 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | LCM. Initialize bank 2 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | TMP. Initialize bank 3 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);

	/*-------------------------------------------------------------------------+
	  | Connector 4~7. Initialize bank 3~ 7 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB4AP,0);
	mtebc(PB4CR,0);
	mtebc(PB5AP,0);
	mtebc(PB5CR,0);
	mtebc(PB6AP,0);
	mtebc(PB6CR,0);
	mtebc(PB7AP,0);
	mtebc(PB7CR,0);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	/*
	 * Because of the interrupt handling rework to handle 440GX interrupts
	 * with the common code, we needed to change names of the UIC registers.
	 * Here the new relationship:
	 *
	 * U-Boot name	440GX name
	 * -----------------------
	 * UIC0		UICB0
	 * UIC1		UIC0
	 * UIC2		UIC1
	 * UIC3		UIC2
	 */
	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
	mtdcr (UIC1ER, 0x00000000);	/* disable all */
	mtdcr (UIC1CR, 0x00000009);	/* SMI & UIC1 crit are critical */
	mtdcr (UIC1PR, 0xfffffe13);	/* per ref-board manual */
	mtdcr (UIC1TR, 0x01c00008);	/* per ref-board manual */
	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC1SR, 0xffffffff);	/* clear all */

	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
	mtdcr (UIC2ER, 0x00000000);	/* disable all */
	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC2PR, 0xffffe0ff);	/* per ref-board manual */
	mtdcr (UIC2TR, 0x00ffc000);	/* per ref-board manual */
	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC2SR, 0xffffffff);	/* clear all */

	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
	mtdcr (UIC3ER, 0x00000000);	/* disable all */
	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC3PR, 0xffffffff);	/* per ref-board manual */
	mtdcr (UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC3SR, 0xffffffff);	/* clear all */

	mtdcr (UIC0SR, 0xfc000000);	/* clear all */
	mtdcr (UIC0ER, 0x00000000);	/* disable all */
	mtdcr (UIC0CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC0PR, 0xfc000000);	/* */
	mtdcr (UIC0TR, 0x00000000);	/* */
	mtdcr (UIC0VR, 0x00000001);	/* */

	/* Enable two GPIO 10~11 and TraceA signal */
	mfsdr(SDR0_PFC0,reg);
	reg |= 0x00300000;
	mtsdr(SDR0_PFC0,reg);

	mfsdr(SDR0_PFC1,reg);
	reg |= 0x00100000;
	mtsdr(SDR0_PFC1,reg);

	/* Set GPIO 10 and 11 as output */
	GpioOdr	= (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
	GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
	GpioOr  = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);

	*GpioOdr &= ~(0x00300000);
	*GpioTcr |= 0x00300000;
	*GpioOr  |= 0x00300000;

	return 0;
}

int misc_init_r(void)
{
	lcd_init();

	return 0;
}

int checkboard (void)
{
	char *s = getenv ("serial#");

	printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
	if (s != NULL) {
		puts (", serial# ");
		puts (s);
	}
	putc ('\n');

#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
	show_reset_reg();
#endif

	return (0);
}

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
	unsigned long strap;

	/*--------------------------------------------------------------------------+
	 *	The ocotea board is always configured as the host & requires the
	 *	PCI arbiter to be enabled.
	 *--------------------------------------------------------------------------*/
	mfsdr(SDR0_SDSTP1, strap);
	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
		return 0;
	}

	return 1;
}
#endif /* defined(CONFIG_PCI) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
	/*--------------------------------------------------------------------------+
	 * Disable everything
	 *--------------------------------------------------------------------------*/
	out32r( PCIX0_PIM0SA, 0 ); /* disable */
	out32r( PCIX0_PIM1SA, 0 ); /* disable */
	out32r( PCIX0_PIM2SA, 0 ); /* disable */
	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */

	/*--------------------------------------------------------------------------+
	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
	 * options to not support sizes such as 128/256 MB.
	 *--------------------------------------------------------------------------*/
	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
	out32r( PCIX0_PIM0LAH, 0 );
	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );

	out32r( PCIX0_BAR0, 0 );

	/*--------------------------------------------------------------------------+
	 * Program the board's subsystem id/vendor id
	 *--------------------------------------------------------------------------*/
	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );

	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
	/* The ocotea board is always configured as host. */
	return(1);
}
#endif /* defined(CONFIG_PCI) */

#ifdef CONFIG_POST
/*
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
int post_hotkeys_pressed(void)
{
	return (ctrlc());
}
#endif

int board_eth_init(bd_t *bis)
{
	cpu_eth_init(bis);
	return pci_eth_init(bis);
}
Commit	Line	Data
5fb692ca SR	1	/*
	2	* Copyright (C) 2004 PaulReynolds@lhsolutions.com
	3	*
	4	* (C) Copyright 2007
	5	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/processor.h>
	28	#include <spd_sdram.h>
	29	#include <ppc4xx_enet.h>
10efa024	30	#include <netdev.h>
5fb692ca	31
6d0f6bcf	32	#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
5fb692ca SR	33	void show_reset_reg(void);
	34	#endif
	35
1218abf1 WD	36	DECLARE_GLOBAL_DATA_PTR;
1218abf1 WD	37
5fb692ca SR	38	int lcd_init(void);
	39
	40	int board_early_init_f (void)
	41	{
	42	unsigned long reg;
	43	volatile unsigned int *GpioOdr;
	44	volatile unsigned int *GpioTcr;
	45	volatile unsigned int *GpioOr;
	46
	47	/*-------------------------------------------------------------------------+
	48	\| Initialize EBC CONFIG
	49	+-------------------------------------------------------------------------*/
d1c3b275	50	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK \|
5fb692ca SR	51	EBC_CFG_PTD_ENABLE \| EBC_CFG_RTC_64PERCLK \|
	52	EBC_CFG_ATC_PREVIOUS \| EBC_CFG_DTC_PREVIOUS \|
	53	EBC_CFG_CTC_PREVIOUS \| EBC_CFG_EMC_DEFAULT \|
	54	EBC_CFG_PME_DISABLE \| EBC_CFG_PR_32);
	55
	56	/*-------------------------------------------------------------------------+
	57	\| 64MB FLASH. Initialize bank 0 with default values.
	58	+-------------------------------------------------------------------------*/
d1c3b275	59	mtebc(PB0AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(15) \|
5fb692ca SR	60	EBC_BXAP_BCE_DISABLE \|
	61	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_OEN_ENCODE(1) \|
	62	EBC_BXAP_WBN_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(1) \|
	63	EBC_BXAP_TH_ENCODE(3) \| EBC_BXAP_RE_DISABLED \|
	64	EBC_BXAP_BEM_WRITEONLY \|
	65	EBC_BXAP_PEN_DISABLED);
d1c3b275	66	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) \|
5fb692ca SR	67	EBC_BXCR_BS_64MB \| EBC_BXCR_BU_RW\|EBC_BXCR_BW_32BIT);
	68
	69	/*-------------------------------------------------------------------------+
	70	\| FPGA. Initialize bank 1 with default values.
	71	+-------------------------------------------------------------------------*/
d1c3b275	72	mtebc(PB1AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(5) \|
5fb692ca SR	73	EBC_BXAP_BCE_DISABLE \|
	74	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_OEN_ENCODE(1) \|
	75	EBC_BXAP_WBN_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(1) \|
	76	EBC_BXAP_TH_ENCODE(3) \| EBC_BXAP_RE_DISABLED \|
	77	EBC_BXAP_BEM_WRITEONLY \|
	78	EBC_BXAP_PEN_DISABLED);
d1c3b275	79	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) \|
5fb692ca SR	80	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT);
	81
	82	/*-------------------------------------------------------------------------+
	83	\| LCM. Initialize bank 2 with default values.
	84	+-------------------------------------------------------------------------*/
d1c3b275	85	mtebc(PB2AP, EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(64) \|
5fb692ca SR	86	EBC_BXAP_BCE_DISABLE \|
	87	EBC_BXAP_CSN_ENCODE(3) \| EBC_BXAP_OEN_ENCODE(3) \|
	88	EBC_BXAP_WBN_ENCODE(3) \| EBC_BXAP_WBF_ENCODE(3) \|
	89	EBC_BXAP_TH_ENCODE(7) \| EBC_BXAP_RE_DISABLED \|
	90	EBC_BXAP_BEM_WRITEONLY \|
	91	EBC_BXAP_PEN_DISABLED);
d1c3b275	92	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) \|
5fb692ca SR	93	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
	94
	95	/*-------------------------------------------------------------------------+
	96	\| TMP. Initialize bank 3 with default values.
	97	+-------------------------------------------------------------------------*/
d1c3b275	98	mtebc(PB3AP, EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(128) \|
5fb692ca SR	99	EBC_BXAP_BCE_DISABLE \|
	100	EBC_BXAP_CSN_ENCODE(3) \| EBC_BXAP_OEN_ENCODE(3) \|
	101	EBC_BXAP_WBN_ENCODE(3) \| EBC_BXAP_WBF_ENCODE(3) \|
	102	EBC_BXAP_TH_ENCODE(7) \| EBC_BXAP_RE_DISABLED \|
	103	EBC_BXAP_BEM_WRITEONLY \|
	104	EBC_BXAP_PEN_DISABLED);
d1c3b275	105	mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) \|
5fb692ca SR	106	EBC_BXCR_BS_64MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
	107
	108	/*-------------------------------------------------------------------------+
	109	\| Connector 4~7. Initialize bank 3~ 7 with default values.
	110	+-------------------------------------------------------------------------*/
d1c3b275 SR	111	mtebc(PB4AP,0);
	112	mtebc(PB4CR,0);
	113	mtebc(PB5AP,0);
	114	mtebc(PB5CR,0);
	115	mtebc(PB6AP,0);
	116	mtebc(PB6CR,0);
	117	mtebc(PB7AP,0);
	118	mtebc(PB7CR,0);
5fb692ca SR	119
	120	/*--------------------------------------------------------------------
	121	* Setup the interrupt controller polarities, triggers, etc.
	122	-------------------------------------------------------------------/
5de85140 SR	123	/*
	124	* Because of the interrupt handling rework to handle 440GX interrupts
	125	* with the common code, we needed to change names of the UIC registers.
	126	* Here the new relationship:
	127	*
	128	* U-Boot name 440GX name
	129	* -----------------------
	130	* UIC0 UICB0
	131	* UIC1 UIC0
	132	* UIC2 UIC1
	133	* UIC3 UIC2
	134	*/
952e7760 SR	135	mtdcr (UIC1SR, 0xffffffff); /* clear all */
	136	mtdcr (UIC1ER, 0x00000000); /* disable all */
	137	mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
	138	mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
	139	mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
	140	mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
	141	mtdcr (UIC1SR, 0xffffffff); /* clear all */
	142
	143	mtdcr (UIC2SR, 0xffffffff); /* clear all */
	144	mtdcr (UIC2ER, 0x00000000); /* disable all */
	145	mtdcr (UIC2CR, 0x00000000); /* all non-critical */
	146	mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
	147	mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
	148	mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
	149	mtdcr (UIC2SR, 0xffffffff); /* clear all */
	150
	151	mtdcr (UIC3SR, 0xffffffff); /* clear all */
	152	mtdcr (UIC3ER, 0x00000000); /* disable all */
	153	mtdcr (UIC3CR, 0x00000000); /* all non-critical */
	154	mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
	155	mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
	156	mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
	157	mtdcr (UIC3SR, 0xffffffff); /* clear all */
	158
	159	mtdcr (UIC0SR, 0xfc000000); /* clear all */
	160	mtdcr (UIC0ER, 0x00000000); /* disable all */
	161	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
	162	mtdcr (UIC0PR, 0xfc000000); /* */
	163	mtdcr (UIC0TR, 0x00000000); /* */
	164	mtdcr (UIC0VR, 0x00000001); /* */
5fb692ca SR	165
5fb692ca SR	166	/* Enable two GPIO 10~11 and TraceA signal */
d1c3b275	167	mfsdr(SDR0_PFC0,reg);
5fb692ca	168	reg \|= 0x00300000;
d1c3b275	169	mtsdr(SDR0_PFC0,reg);
5fb692ca	170
d1c3b275	171	mfsdr(SDR0_PFC1,reg);
5fb692ca	172	reg \|= 0x00100000;
d1c3b275	173	mtsdr(SDR0_PFC1,reg);
5fb692ca SR	174
5fb692ca SR	175	/* Set GPIO 10 and 11 as output */
6d0f6bcf JCPV	176	GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
	177	GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
	178	GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);
5fb692ca SR	179
	180	*GpioOdr &= ~(0x00300000);
	181	*GpioTcr \|= 0x00300000;
a4012396	182	*GpioOr \|= 0x00300000;
5fb692ca SR	183
	184	return 0;
	185	}
	186
	187	int misc_init_r(void)
	188	{
	189	lcd_init();
	190
	191	return 0;
	192	}
	193
	194	int checkboard (void)
	195	{
	196	char *s = getenv ("serial#");
	197
	198	printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
	199	if (s != NULL) {
	200	puts (", serial# ");
	201	puts (s);
	202	}
	203	putc ('\n');
	204
6d0f6bcf	205	#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
5fb692ca SR	206	show_reset_reg();
	207	#endif
	208
	209	return (0);
	210	}
	211
5fb692ca SR	212	/*************************************************************************
	213	* pci_pre_init
	214	*
	215	* This routine is called just prior to registering the hose and gives
	216	* the board the opportunity to check things. Returning a value of zero
	217	* indicates that things are bad & PCI initialization should be aborted.
	218	*
	219	* Different boards may wish to customize the pci controller structure
	220	* (add regions, override default access routines, etc) or perform
	221	* certain pre-initialization actions.
	222	*
	223	************************************************************************/
466fff1a	224	#if defined(CONFIG_PCI)
5fb692ca SR	225	int pci_pre_init(struct pci_controller * hose )
	226	{
	227	unsigned long strap;
	228
	229	/*--------------------------------------------------------------------------+
	230	* The ocotea board is always configured as the host & requires the
	231	* PCI arbiter to be enabled.
	232	--------------------------------------------------------------------------/
d1c3b275	233	mfsdr(SDR0_SDSTP1, strap);
5fb692ca SR	234	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
	235	printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
	236	return 0;
	237	}
	238
	239	return 1;
	240	}
466fff1a	241	#endif /* defined(CONFIG_PCI) */
5fb692ca SR	242
	243	/*************************************************************************
	244	* pci_target_init
	245	*
	246	* The bootstrap configuration provides default settings for the pci
	247	* inbound map (PIM). But the bootstrap config choices are limited and
	248	* may not be sufficient for a given board.
	249	*
	250	************************************************************************/
6d0f6bcf	251	#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
5fb692ca SR	252	void pci_target_init(struct pci_controller * hose )
5fb692ca SR	253	{
5fb692ca SR	254	/*--------------------------------------------------------------------------+
	255	* Disable everything
	256	--------------------------------------------------------------------------/
	257	out32r( PCIX0_PIM0SA, 0 ); /* disable */
	258	out32r( PCIX0_PIM1SA, 0 ); /* disable */
	259	out32r( PCIX0_PIM2SA, 0 ); /* disable */
	260	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
	261
	262	/*--------------------------------------------------------------------------+
	263	* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
	264	* options to not support sizes such as 128/256 MB.
	265	--------------------------------------------------------------------------/
6d0f6bcf	266	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
5fb692ca SR	267	out32r( PCIX0_PIM0LAH, 0 );
	268	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) \| 1 );
	269
	270	out32r( PCIX0_BAR0, 0 );
	271
	272	/*--------------------------------------------------------------------------+
	273	* Program the board's subsystem id/vendor id
	274	--------------------------------------------------------------------------/
6d0f6bcf JCPV	275	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
6d0f6bcf JCPV	276	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
5fb692ca SR	277
	278	out16r( PCIX0_CMD, in16r(PCIX0_CMD) \| PCI_COMMAND_MEMORY );
	279	}
6d0f6bcf	280	#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
5fb692ca SR	281
	282	/*************************************************************************
	283	* is_pci_host
	284	*
	285	* This routine is called to determine if a pci scan should be
	286	* performed. With various hardware environments (especially cPCI and
	287	* PPMC) it's insufficient to depend on the state of the arbiter enable
	288	* bit in the strap register, or generic host/adapter assumptions.
	289	*
	290	* Rather than hard-code a bad assumption in the general 440 code, the
	291	* 440 pci code requires the board to decide at runtime.
	292	*
	293	* Return 0 for adapter mode, non-zero for host (monarch) mode.
	294	*
	295	*
	296	************************************************************************/
	297	#if defined(CONFIG_PCI)
	298	int is_pci_host(struct pci_controller *hose)
	299	{
	300	/* The ocotea board is always configured as host. */
	301	return(1);
	302	}
	303	#endif /* defined(CONFIG_PCI) */
	304
	305	#ifdef CONFIG_POST
	306	/*
	307	* Returns 1 if keys pressed to start the power-on long-running tests
	308	* Called from board_init_f().
	309	*/
	310	int post_hotkeys_pressed(void)
	311	{
	312	return (ctrlc());
	313	}
	314	#endif
10efa024 BW	315
	316	int board_eth_init(bd_t *bis)
	317	{
cef0efaf	318	cpu_eth_init(bis);
10efa024 BW	319	return pci_eth_init(bis);
10efa024 BW	320	}