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8a316c9b SR |
1 | /* |
2 | * (C) Copyright 2000-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/processor.h> | |
26 | #include <spd_sdram.h> | |
27 | ||
28 | int board_early_init_f(void) | |
29 | { | |
30 | /*-------------------------------------------------------------------------+ | |
31 | | Interrupt controller setup for the Walnut/Sycamore board. | |
32 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
33 | | IRQ 16 405GP internally generated; active low; level sensitive | |
34 | | IRQ 17-24 RESERVED | |
35 | | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive | |
36 | | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive | |
37 | | IRQ 27 (EXT IRQ 2) Not Used | |
38 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive | |
39 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
40 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive | |
41 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive | |
42 | | Note for Walnut board: | |
43 | | An interrupt taken for the FPGA (IRQ 25) indicates that either | |
44 | | the Mouse, Keyboard, IRDA, or External Expansion caused the | |
45 | | interrupt. The FPGA must be read to determine which device | |
46 | | caused the interrupt. The default setting of the FPGA clears | |
47 | | | |
48 | +-------------------------------------------------------------------------*/ | |
49 | ||
50 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
51 | mtdcr(uicer, 0x00000000); /* disable all ints */ | |
52 | mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ | |
53 | mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */ | |
54 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ | |
55 | mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
56 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
57 | ||
58 | /* set UART1 control to select CTS/RTS */ | |
59 | #define FPGA_BRDC 0xF0300004 | |
60 | *(volatile char *)(FPGA_BRDC) |= 0x1; | |
61 | ||
62 | return 0; | |
63 | } | |
64 | ||
65 | /* | |
66 | * Check Board Identity: | |
67 | */ | |
68 | int checkboard(void) | |
69 | { | |
77ddac94 | 70 | char *s = getenv("serial#"); |
8a316c9b SR |
71 | uint pvr = get_pvr(); |
72 | ||
73 | if (pvr == PVR_405GPR_RB) { | |
74 | puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board"); | |
75 | } else { | |
76 | puts("Board: Walnut - AMCC PPC405GP Evaluation Board"); | |
77 | } | |
78 | ||
79 | if (s != NULL) { | |
80 | puts(", serial# "); | |
81 | puts(s); | |
82 | } | |
83 | putc('\n'); | |
84 | ||
85 | return (0); | |
86 | } | |
87 | ||
8a316c9b SR |
88 | /* |
89 | * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of | |
90 | * the necessary info for SDRAM controller configuration | |
91 | */ | |
92 | long int initdram(int board_type) | |
93 | { | |
d87080b7 | 94 | return spd_sdram(); |
8a316c9b | 95 | } |