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Commit | Line | Data |
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8a316c9b SR |
1 | /* |
2 | * (C) Copyright 2000-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
8a316c9b SR |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/processor.h> | |
10 | #include <spd_sdram.h> | |
11 | ||
088454cd SG |
12 | DECLARE_GLOBAL_DATA_PTR; |
13 | ||
8a316c9b SR |
14 | int board_early_init_f(void) |
15 | { | |
16 | /*-------------------------------------------------------------------------+ | |
17 | | Interrupt controller setup for the Walnut/Sycamore board. | |
18 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
19 | | IRQ 16 405GP internally generated; active low; level sensitive | |
20 | | IRQ 17-24 RESERVED | |
21 | | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive | |
22 | | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive | |
23 | | IRQ 27 (EXT IRQ 2) Not Used | |
24 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive | |
25 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
26 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive | |
27 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive | |
28 | | Note for Walnut board: | |
29 | | An interrupt taken for the FPGA (IRQ 25) indicates that either | |
30 | | the Mouse, Keyboard, IRDA, or External Expansion caused the | |
31 | | interrupt. The FPGA must be read to determine which device | |
32 | | caused the interrupt. The default setting of the FPGA clears | |
33 | | | |
34 | +-------------------------------------------------------------------------*/ | |
35 | ||
952e7760 SR |
36 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
37 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ | |
38 | mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ | |
39 | mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */ | |
40 | mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ | |
41 | mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
42 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
8a316c9b SR |
43 | |
44 | /* set UART1 control to select CTS/RTS */ | |
45 | #define FPGA_BRDC 0xF0300004 | |
46 | *(volatile char *)(FPGA_BRDC) |= 0x1; | |
47 | ||
48 | return 0; | |
49 | } | |
50 | ||
51 | /* | |
52 | * Check Board Identity: | |
53 | */ | |
54 | int checkboard(void) | |
55 | { | |
f0c0b3a9 WD |
56 | char buf[64]; |
57 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
8a316c9b SR |
58 | uint pvr = get_pvr(); |
59 | ||
60 | if (pvr == PVR_405GPR_RB) { | |
61 | puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board"); | |
62 | } else { | |
63 | puts("Board: Walnut - AMCC PPC405GP Evaluation Board"); | |
64 | } | |
65 | ||
f0c0b3a9 | 66 | if (i > 0) { |
8a316c9b | 67 | puts(", serial# "); |
f0c0b3a9 | 68 | puts(buf); |
8a316c9b SR |
69 | } |
70 | putc('\n'); | |
71 | ||
72 | return (0); | |
73 | } | |
74 | ||
8a316c9b | 75 | /* |
f1683aa7 | 76 | * dram_init() reads EEPROM via I2c. EEPROM contains all of |
8a316c9b SR |
77 | * the necessary info for SDRAM controller configuration |
78 | */ | |
f1683aa7 | 79 | int dram_init(void) |
8a316c9b | 80 | { |
088454cd SG |
81 | gd->ram_size = spd_sdram(); |
82 | ||
83 | return 0; | |
8a316c9b | 84 | } |