[people/ms/u-boot.git] / board / amcc / yosemite / yosemite.c

/*
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <spd_sdram.h>

extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/

int board_early_init_f(void)
{
	register uint reg;

	/*--------------------------------------------------------------------
	 * Setup the external bus controller/chip selects
	 *-------------------------------------------------------------------*/
	mtdcr(ebccfga, xbcfg);
	reg = mfdcr(ebccfgd);
	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */

	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */
	mtebc(pb0cr, 0xfc0da000);	/* BAS=0xfc0 64MB r/w 16-bit */

	mtebc(pb1ap, 0x00000000);
	mtebc(pb1cr, 0x00000000);

	mtebc(pb2ap, 0x04814500);
	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */

	mtebc(pb3ap, 0x00000000);
	mtebc(pb3cr, 0x00000000);

	mtebc(pb4ap, 0x00000000);
	mtebc(pb4cr, 0x00000000);

	mtebc(pb5ap, 0x00000000);
	mtebc(pb5cr, 0x00000000);

	/*--------------------------------------------------------------------
	 * Setup the GPIO pins
	 *-------------------------------------------------------------------*/
	/*CPLD cs */
	/*setup Address lines for flash sizes larger than 16Meg. */
	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);

	/*setup emac */
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);

	/*UART1 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);

	/* external interrupts IRQ0...3 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);

	/*setup USB 2.0 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr(uic0sr, 0xffffffff);	/* clear all */
	mtdcr(uic0er, 0x00000000);	/* disable all */
	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic0sr, 0xffffffff);	/* clear all */

	mtdcr(uic1sr, 0xffffffff);	/* clear all */
	mtdcr(uic1er, 0x00000000);	/* disable all */
	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic1sr, 0xffffffff);	/* clear all */

	/*--------------------------------------------------------------------
	 * Setup other serial configuration
	 *-------------------------------------------------------------------*/
	mfsdr(sdr_pci0, reg);
	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */
	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */

	/*clear tmrclk divisor */
	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;

	/*enable ethernet */
	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;

	/*enable usb 1.1 fs device and remove usb 2.0 reset */
	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;

	/*get rid of flash write protect */
	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;

	return 0;
}

int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;
	uint pbcr;
	int size_val = 0;

	/* Re-do sizing to get full correct info */
	mtdcr(ebccfga, pb0cr);
	pbcr = mfdcr(ebccfgd);
	switch (gd->bd->bi_flashsize) {
	case 1 << 20:
		size_val = 0;
		break;
	case 2 << 20:
		size_val = 1;
		break;
	case 4 << 20:
		size_val = 2;
		break;
	case 8 << 20:
		size_val = 3;
		break;
	case 16 << 20:
		size_val = 4;
		break;
	case 32 << 20:
		size_val = 5;
		break;
	case 64 << 20:
		size_val = 6;
		break;
	case 128 << 20:
		size_val = 7;
		break;
	}
	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
	mtdcr(ebccfga, pb0cr);
	mtdcr(ebccfgd, pbcr);

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/* Monitor protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    -CFG_MONITOR_LEN,
			    0xffffffff,
			    &flash_info[0]);

	return 0;
}

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

/*************************************************************************
 *  sdram_init -- doesn't use serial presence detect.
 *
 *  Assumes:    256 MB, ECC, non-registered
 *              PLB @ 133 MHz
 *
 ************************************************************************/
void sdram_init(void)
{
	register uint reg;

	/*--------------------------------------------------------------------
	 * Setup some default
	 *------------------------------------------------------------------*/
	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
	mtsdram(mem_clktr, 0x40000000);	/* ?? */
	mtsdram(mem_wddctr, 0x40000000);	/* ?? */

	/*clear this first, if the DDR is enabled by a debugger
	   then you can not make changes. */
	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */

	/*--------------------------------------------------------------------
	 * Setup for board-specific specific mem
	 *------------------------------------------------------------------*/
	/*
	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
	 */
	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */

	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
	mtsdram(mem_tr1, 0x8080080b);	/* ?? */
	mtsdram(mem_rtr, 0x04080000);	/* ?? */
	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
	mtsdram(mem_cfg0, 0x34000000);	/* Disable EEC */
	udelay(400);		/* Delay 200 usecs (min)            */

	/*--------------------------------------------------------------------
	 * Enable the controller, then wait for DCEN to complete
	 *------------------------------------------------------------------*/
	mtsdram(mem_cfg0, 0x84000000);	/* Enable */

	for (;;) {
		mfsdram(mem_mcsts, reg);
		if (reg & 0x80000000)
			break;
	}
}

/*************************************************************************
 *  long int initdram
 *
 ************************************************************************/
long int initdram(int board)
{
	sdram_init();
	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);	/* return bytes */
}

#if defined(CFG_DRAM_TEST)
int testdram(void)
{
	unsigned long *mem = (unsigned long *)0;
	const unsigned long kend = (1024 / sizeof(unsigned long));
	unsigned long k, n;

	mtmsr(0);

	for (k = 0; k < CFG_KBYTES_SDRAM;
	     ++k, mem += (1024 / sizeof(unsigned long))) {
		if ((k & 1023) == 0) {
			printf("%3d MB\r", k / 1024);
		}

		memset(mem, 0xaaaaaaaa, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0xaaaaaaaa) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}

		memset(mem, 0x55555555, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0x55555555) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}
	}
	printf("SDRAM test passes\n");
	return 0;
}
#endif

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
	unsigned long addr;

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB3 devices to 0.
	  | Set PLB3 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp1, addr);
	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb3_acr);
	mtdcr(plb3_acr, addr | 0x80000000);

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB4 devices to 0.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp0, addr);
	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
	mtdcr(plb4_acr, addr);

	/*-------------------------------------------------------------------------+
	  | Set Nebula PLB4 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	/* Segment0 */
	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
	mtdcr(plb0_acr, addr);

	/* Segment1 */
	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
	mtdcr(plb1_acr, addr);

	return 1;
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
	/*--------------------------------------------------------------------------+
	 * Set up Direct MMIO registers
	 *--------------------------------------------------------------------------*/
	/*--------------------------------------------------------------------------+
	  | PowerPC440 EP PCI Master configuration.
	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	  |   Use byte reversed out routines to handle endianess.
	  | Make this region non-prefetchable.
	  +--------------------------------------------------------------------------*/
	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */

	/*--------------------------------------------------------------------------+
	 * Set up Configuration registers
	 *--------------------------------------------------------------------------*/

	/* Program the board's subsystem id/vendor id */
	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
			      CFG_PCI_SUBSYS_VENDORID);
	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);

	/* Configure command register as bus master */
	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);

	/* 240nS PCI clock */
	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);

	/* No error reporting */
	pci_write_config_word(0, PCI_ERREN, 0);

	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);

}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

/*************************************************************************
 *  pci_master_init
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
	unsigned short temp_short;

	/*--------------------------------------------------------------------------+
	  | Write the PowerPC440 EP PCI Configuration regs.
	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
	  +--------------------------------------------------------------------------*/
	pci_read_config_word(0, PCI_COMMAND, &temp_short);
	pci_write_config_word(0, PCI_COMMAND,
			      temp_short | PCI_COMMAND_MASTER |
			      PCI_COMMAND_MEMORY);
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
	/* Bamboo is always configured as host. */
	return (1);
}
#endif				/* defined(CONFIG_PCI) */

/*************************************************************************
 *  hw_watchdog_reset
 *
 *	This routine is called to reset (keep alive) the watchdog timer
 *
 ************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{

}
#endif
Commit	Line	Data
c157d8e2 SR	1	/*
	2	*
	3	* See file CREDITS for list of people who contributed to this
	4	* project.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include <common.h>
84286386	23	#include <ppc4xx.h>
c157d8e2 SR	24	#include <asm/processor.h>
	25	#include <spd_sdram.h>
	26
84286386 SR	27	extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
84286386 SR	28
c157d8e2 SR	29	int board_early_init_f(void)
	30	{
	31	register uint reg;
	32
	33	/*--------------------------------------------------------------------
	34	* Setup the external bus controller/chip selects
	35	-------------------------------------------------------------------/
	36	mtdcr(ebccfga, xbcfg);
	37	reg = mfdcr(ebccfgd);
	38	mtdcr(ebccfgd, reg \| 0x04000000); /* Set ATC */
	39
	40	mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
84286386	41	mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
c157d8e2 SR	42
	43	mtebc(pb1ap, 0x00000000);
	44	mtebc(pb1cr, 0x00000000);
	45
	46	mtebc(pb2ap, 0x04814500);
	47	/CPLD/ mtebc(pb2cr, 0x80018000); /BAS=0x800 1MB r/w 8-bit /
	48
	49	mtebc(pb3ap, 0x00000000);
	50	mtebc(pb3cr, 0x00000000);
	51
	52	mtebc(pb4ap, 0x00000000);
	53	mtebc(pb4cr, 0x00000000);
	54
	55	mtebc(pb5ap, 0x00000000);
	56	mtebc(pb5cr, 0x00000000);
	57
c157d8e2 SR	58	/*--------------------------------------------------------------------
	59	* Setup the GPIO pins
	60	-------------------------------------------------------------------/
	61	/CPLD cs /
	62	/setup Address lines for flash sizes larger than 16Meg. /
	63	out32(GPIO0_OSRL, in32(GPIO0_OSRL) \| 0x40010000);
	64	out32(GPIO0_TSRL, in32(GPIO0_TSRL) \| 0x40010000);
	65	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) \| 0x40000000);
	66
	67	/setup emac /
	68	out32(GPIO0_TCR, in32(GPIO0_TCR) \| 0xC080);
	69	out32(GPIO0_TSRL, in32(GPIO0_TSRL) \| 0x40);
	70	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) \| 0x55);
	71	out32(GPIO0_OSRH, in32(GPIO0_OSRH) \| 0x50004000);
	72	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) \| 0x00440000);
	73
	74	/UART1 /
	75	out32(GPIO1_TCR, in32(GPIO1_TCR) \| 0x02000000);
	76	out32(GPIO1_OSRL, in32(GPIO1_OSRL) \| 0x00080000);
	77	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) \| 0x00010000);
	78
e190290b SR	79	/* external interrupts IRQ0...3 */
	80	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
	81	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
	82	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) \| 0x00005500);
	83
c157d8e2 SR	84	/setup USB 2.0 /
	85	out32(GPIO1_TCR, in32(GPIO1_TCR) \| 0xc0000000);
	86	out32(GPIO1_OSRL, in32(GPIO1_OSRL) \| 0x50000000);
	87	out32(GPIO0_TCR, in32(GPIO0_TCR) \| 0xf);
	88	out32(GPIO0_OSRH, in32(GPIO0_OSRH) \| 0xaa);
	89	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) \| 0x00000500);
	90
ef04a0aa SR	91	/*--------------------------------------------------------------------
	92	* Setup the interrupt controller polarities, triggers, etc.
	93	-------------------------------------------------------------------/
	94	mtdcr(uic0sr, 0xffffffff); /* clear all */
	95	mtdcr(uic0er, 0x00000000); /* disable all */
	96	mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
	97	mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
	98	mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
	99	mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
	100	mtdcr(uic0sr, 0xffffffff); /* clear all */
	101
	102	mtdcr(uic1sr, 0xffffffff); /* clear all */
	103	mtdcr(uic1er, 0x00000000); /* disable all */
	104	mtdcr(uic1cr, 0x00000000); /* all non-critical */
	105	mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
	106	mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
	107	mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
	108	mtdcr(uic1sr, 0xffffffff); /* clear all */
	109
c157d8e2 SR	110	/*--------------------------------------------------------------------
	111	* Setup other serial configuration
	112	-------------------------------------------------------------------/
	113	mfsdr(sdr_pci0, reg);
	114	mtsdr(sdr_pci0, 0x80000000 \| reg); /* PCI arbiter enabled */
	115	mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
	116	mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
	117
	118	/clear tmrclk divisor /
	119	(unsigned char )(CFG_BCSR_BASE \| 0x04) = 0x00;
	120
	121	/enable ethernet /
	122	(unsigned char )(CFG_BCSR_BASE \| 0x08) = 0xf0;
	123
	124	/enable usb 1.1 fs device and remove usb 2.0 reset /
	125	(unsigned char )(CFG_BCSR_BASE \| 0x09) = 0x00;
	126
	127	/get rid of flash write protect /
	128	(unsigned char )(CFG_BCSR_BASE \| 0x07) = 0x40;
	129
	130	return 0;
	131	}
	132
84286386 SR	133	int misc_init_r (void)
	134	{
	135	DECLARE_GLOBAL_DATA_PTR;
	136	uint pbcr;
	137	int size_val = 0;
	138
	139	/* Re-do sizing to get full correct info */
	140	mtdcr(ebccfga, pb0cr);
	141	pbcr = mfdcr(ebccfgd);
	142	switch (gd->bd->bi_flashsize) {
	143	case 1 << 20:
	144	size_val = 0;
	145	break;
	146	case 2 << 20:
	147	size_val = 1;
	148	break;
	149	case 4 << 20:
	150	size_val = 2;
	151	break;
	152	case 8 << 20:
	153	size_val = 3;
	154	break;
	155	case 16 << 20:
	156	size_val = 4;
	157	break;
	158	case 32 << 20:
	159	size_val = 5;
	160	break;
	161	case 64 << 20:
	162	size_val = 6;
	163	break;
	164	case 128 << 20:
	165	size_val = 7;
	166	break;
	167	}
	168	pbcr = (pbcr & 0x0001ffff) \| gd->bd->bi_flashstart \| (size_val << 17);
	169	mtdcr(ebccfga, pb0cr);
	170	mtdcr(ebccfgd, pbcr);
	171
f190c11b SR	172	/* adjust flash start and offset */
	173	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	174	gd->bd->bi_flashoffset = 0;
	175
84286386 SR	176	/* Monitor protection ON by default */
	177	(void)flash_protect(FLAG_PROTECT_SET,
	178	-CFG_MONITOR_LEN,
	179	0xffffffff,
	180	&flash_info[0]);
	181
	182	return 0;
	183	}
	184
c157d8e2 SR	185	int checkboard(void)
c157d8e2 SR	186	{
3d9569b2	187	char *s = getenv("serial#");
c157d8e2	188
93b17ec3 SR	189	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
	190	if (s != NULL) {
	191	puts(", serial# ");
	192	puts(s);
	193	}
	194	putc('\n');
	195
c157d8e2 SR	196	return (0);
	197	}
	198
	199	/*************************************************************************
	200	* sdram_init -- doesn't use serial presence detect.
	201	*
	202	* Assumes: 256 MB, ECC, non-registered
	203	* PLB @ 133 MHz
	204	*
	205	************************************************************************/
	206	void sdram_init(void)
	207	{
	208	register uint reg;
	209
	210	/*--------------------------------------------------------------------
	211	* Setup some default
	212	------------------------------------------------------------------/
	213	mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
	214	mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
	215	mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
	216	mtsdram(mem_clktr, 0x40000000); /* ?? */
	217	mtsdram(mem_wddctr, 0x40000000); /* ?? */
	218
	219	/*clear this first, if the DDR is enabled by a debugger
	220	then you can not make changes. */
	221	mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
	222
	223	/*--------------------------------------------------------------------
	224	* Setup for board-specific specific mem
	225	------------------------------------------------------------------/
	226	/*
	227	* Following for CAS Latency = 2.5 @ 133 MHz PLB
	228	*/
	229	mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
	230	mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
	231
	232	mtsdram(mem_tr0, 0x410a4012); /* ?? */
	233	mtsdram(mem_tr1, 0x8080080b); /* ?? */
	234	mtsdram(mem_rtr, 0x04080000); /* ?? */
	235	mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
	236	mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
	237	udelay(400); /* Delay 200 usecs (min) */
	238
	239	/*--------------------------------------------------------------------
	240	* Enable the controller, then wait for DCEN to complete
	241	------------------------------------------------------------------/
	242	mtsdram(mem_cfg0, 0x84000000); /* Enable */
	243
	244	for (;;) {
	245	mfsdram(mem_mcsts, reg);
	246	if (reg & 0x80000000)
	247	break;
	248	}
	249	}
	250
	251	/*************************************************************************
	252	* long int initdram
	253	*
	254	************************************************************************/
	255	long int initdram(int board)
	256	{
	257	sdram_init();
	258	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
	259	}
260
261	#if defined(CFG_DRAM_TEST)
262	int testdram(void)
263	{
264	unsigned long mem = (unsigned long )0;
265	const unsigned long kend = (1024 / sizeof(unsigned long));
266	unsigned long k, n;
267
268	mtmsr(0);
269
270	for (k = 0; k < CFG_KBYTES_SDRAM;
271	++k, mem += (1024 / sizeof(unsigned long))) {
272	if ((k & 1023) == 0) {
273	printf("%3d MB\r", k / 1024);
274	}
275
276	memset(mem, 0xaaaaaaaa, 1024);
277	for (n = 0; n < kend; ++n) {
278	if (mem[n] != 0xaaaaaaaa) {
279	printf("SDRAM test fails at: %08x\n",
280	(uint) & mem[n]);
281	return 1;
282	}
283	}
284
285	memset(mem, 0x55555555, 1024);
286	for (n = 0; n < kend; ++n) {
287	if (mem[n] != 0x55555555) {
288	printf("SDRAM test fails at: %08x\n",
289	(uint) & mem[n]);
290	return 1;
291	}
292	}
293	}
294	printf("SDRAM test passes\n");
295	return 0;
296	}
297	#endif
298
299	/*************************************************************************
300	* pci_pre_init
301	*
302	* This routine is called just prior to registering the hose and gives
303	* the board the opportunity to check things. Returning a value of zero
304	* indicates that things are bad & PCI initialization should be aborted.
305	*
306	* Different boards may wish to customize the pci controller structure
307	* (add regions, override default access routines, etc) or perform
308	* certain pre-initialization actions.
309	*
310	************************************************************************/
311	#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
312	int pci_pre_init(struct pci_controller *hose)
313	{
c157d8e2 SR	314	unsigned long addr;
c157d8e2 SR	315
c157d8e2 SR	316	/*-------------------------------------------------------------------------+
	317	\| Set priority for all PLB3 devices to 0.
	318	\| Set PLB3 arbiter to fair mode.
	319	+-------------------------------------------------------------------------*/
	320	mfsdr(sdr_amp1, addr);
	321	mtsdr(sdr_amp1, (addr & 0x000000FF) \| 0x0000FF00);
	322	addr = mfdcr(plb3_acr);
	323	mtdcr(plb3_acr, addr \| 0x80000000);
	324
	325	/*-------------------------------------------------------------------------+
	326	\| Set priority for all PLB4 devices to 0.
	327	+-------------------------------------------------------------------------*/
	328	mfsdr(sdr_amp0, addr);
	329	mtsdr(sdr_amp0, (addr & 0x000000FF) \| 0x0000FF00);
	330	addr = mfdcr(plb4_acr) \| 0xa0000000; /* Was 0x8---- */
	331	mtdcr(plb4_acr, addr);
	332
	333	/*-------------------------------------------------------------------------+
	334	\| Set Nebula PLB4 arbiter to fair mode.
	335	+-------------------------------------------------------------------------*/
	336	/* Segment0 */
	337	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) \| plb0_acr_ppm_fair;
	338	addr = (addr & ~plb0_acr_hbu_mask) \| plb0_acr_hbu_enabled;
	339	addr = (addr & ~plb0_acr_rdp_mask) \| plb0_acr_rdp_4deep;
	340	addr = (addr & ~plb0_acr_wrp_mask) \| plb0_acr_wrp_2deep;
	341	mtdcr(plb0_acr, addr);
	342
	343	/* Segment1 */
	344	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) \| plb1_acr_ppm_fair;
	345	addr = (addr & ~plb1_acr_hbu_mask) \| plb1_acr_hbu_enabled;
	346	addr = (addr & ~plb1_acr_rdp_mask) \| plb1_acr_rdp_4deep;
	347	addr = (addr & ~plb1_acr_wrp_mask) \| plb1_acr_wrp_2deep;
	348	mtdcr(plb1_acr, addr);
	349
	350	return 1;
	351	}
	352	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
	353
	354	/*************************************************************************
	355	* pci_target_init
	356	*
	357	* The bootstrap configuration provides default settings for the pci
	358	* inbound map (PIM). But the bootstrap config choices are limited and
	359	* may not be sufficient for a given board.
	360	*
	361	************************************************************************/
	362	#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
	363	void pci_target_init(struct pci_controller *hose)
	364	{
	365	/*--------------------------------------------------------------------------+
	366	* Set up Direct MMIO registers
	367	--------------------------------------------------------------------------/
	368	/*--------------------------------------------------------------------------+
	369	\| PowerPC440 EP PCI Master configuration.
	370	\| Map one 1Gig range of PLB/processor addresses to PCI memory space.
	371	\| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	372	\| Use byte reversed out routines to handle endianess.
	373	\| Make this region non-prefetchable.
	374	+--------------------------------------------------------------------------*/
	375	out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
	376	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
	377	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
	378	out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
	379	out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
380
381	out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
382	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
383	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
384	out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
385	out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
386
387	out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
388	out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
389	out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
390	out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
391
392	/*--------------------------------------------------------------------------+
393	* Set up Configuration registers
394	--------------------------------------------------------------------------/
395
396	/* Program the board's subsystem id/vendor id */
397	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
398	CFG_PCI_SUBSYS_VENDORID);
399	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
400
401	/* Configure command register as bus master */
402	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
403
404	/* 240nS PCI clock */
405	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
406
407	/* No error reporting */
408	pci_write_config_word(0, PCI_ERREN, 0);
409
410	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
411
412	}
413	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
414
415	/*************************************************************************
416	* pci_master_init
417	*
418	************************************************************************/
419	#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
420	void pci_master_init(struct pci_controller *hose)
421	{
422	unsigned short temp_short;
423
424	/*--------------------------------------------------------------------------+
425	\| Write the PowerPC440 EP PCI Configuration regs.
426	\| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
427	\| Enable PowerPC440 EP to act as a PCI memory target (PTM).
428	+--------------------------------------------------------------------------*/
429	pci_read_config_word(0, PCI_COMMAND, &temp_short);
430	pci_write_config_word(0, PCI_COMMAND,
431	temp_short \| PCI_COMMAND_MASTER \|
432	PCI_COMMAND_MEMORY);
433	}
434	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
435
436	/*************************************************************************
437	* is_pci_host
438	*
439	* This routine is called to determine if a pci scan should be
440	* performed. With various hardware environments (especially cPCI and
441	* PPMC) it's insufficient to depend on the state of the arbiter enable
442	* bit in the strap register, or generic host/adapter assumptions.
443	*
444	* Rather than hard-code a bad assumption in the general 440 code, the
445	* 440 pci code requires the board to decide at runtime.
446	*
447	* Return 0 for adapter mode, non-zero for host (monarch) mode.
448	*
449	*
450	************************************************************************/
451	#if defined(CONFIG_PCI)
452	int is_pci_host(struct pci_controller *hose)
453	{
454	/* Bamboo is always configured as host. */
455	return (1);
456	}
457	#endif /* defined(CONFIG_PCI) */
458
459	/*************************************************************************
460	* hw_watchdog_reset
461	*
462	* This routine is called to reset (keep alive) the watchdog timer
463	*
464	************************************************************************/
465	#if defined(CONFIG_HW_WATCHDOG)
466	void hw_watchdog_reset(void)
467	{
468
469	}
470	#endif