projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6c5879f3 MB |
1 | /* |
| 2 | * (C) Copyright 2006 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 6c5879f3 | 5 | * Port to AMCC-440SPE Evaluation Board SOP - April 2005 |
| 692519b1 RJ |
6 | * |
| 7 | * PCIe supporting routines derived from Linux 440SPe PCIe driver. | |
| 1a459660 WD |
8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0+ | |
| 6c5879f3 MB |
10 | */ |
| 11 | ||
| 12 | #include <common.h> | |
| b36df561 | 13 | #include <asm/ppc4xx.h> |
| 6c5879f3 | 14 | #include <i2c.h> |
| 10efa024 | 15 | #include <netdev.h> |
| c7c6da23 SR |
16 | #include <asm/processor.h> |
| 17 | #include <asm/io.h> | |
| 18 | #include <asm/4xx_pcie.h> | |
| 1221ce45 | 19 | #include <linux/errno.h> |
| 692519b1 | 20 | |
| 6c5879f3 | 21 | #include "yucca.h" |
| 2b393b0f | 22 | |
| 1218abf1 WD |
23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | ||
| 6c5879f3 | 25 | void fpga_init (void); |
| 6c5879f3 MB |
26 | |
| 27 | #define DEBUG_ENV | |
| 28 | #ifdef DEBUG_ENV | |
| 29 | #define DEBUGF(fmt,args...) printf(fmt ,##args) | |
| 30 | #else | |
| 31 | #define DEBUGF(fmt,args...) | |
| 32 | #endif | |
| 33 | ||
| 6c5879f3 MB |
34 | int board_early_init_f (void) |
| 35 | { | |
| 36 | /*----------------------------------------------------------------------------+ | |
| 37 | | Define Boot devices | |
| 38 | +----------------------------------------------------------------------------*/ | |
| 39 | #define BOOT_FROM_SMALL_FLASH 0x00 | |
| 40 | #define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 | |
| 41 | #define BOOT_FROM_PCI 0x02 | |
| 42 | #define BOOT_DEVICE_UNKNOWN 0x03 | |
| 43 | ||
| 44 | /*----------------------------------------------------------------------------+ | |
| 45 | | EBC Devices Characteristics | |
| 46 | | Peripheral Bank Access Parameters - EBC_BxAP | |
| 47 | | Peripheral Bank Configuration Register - EBC_BxCR | |
| 48 | +----------------------------------------------------------------------------*/ | |
| 49 | ||
| 50 | /* | |
| 51 | * Small Flash and FRAM | |
| 52 | * BU Value | |
| 53 | * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 | |
| 54 | * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000 | |
| 55 | * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000 | |
| 56 | */ | |
| 57 | #define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \ | |
| 58 | EBC_BXAP_TWT_ENCODE(7) | \ | |
| 59 | EBC_BXAP_BCE_DISABLE | \ | |
| 60 | EBC_BXAP_BCT_2TRANS | \ | |
| 61 | EBC_BXAP_CSN_ENCODE(0) | \ | |
| 62 | EBC_BXAP_OEN_ENCODE(0) | \ | |
| 63 | EBC_BXAP_WBN_ENCODE(0) | \ | |
| 64 | EBC_BXAP_WBF_ENCODE(0) | \ | |
| 65 | EBC_BXAP_TH_ENCODE(0) | \ | |
| 66 | EBC_BXAP_RE_DISABLED | \ | |
| 67 | EBC_BXAP_SOR_DELAYED | \ | |
| 68 | EBC_BXAP_BEM_WRITEONLY | \ | |
| 69 | EBC_BXAP_PEN_DISABLED | |
| 70 | ||
| 71 | #define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ | |
| 72 | EBC_BXCR_BS_16MB | \ | |
| 73 | EBC_BXCR_BU_RW | \ | |
| 74 | EBC_BXCR_BW_8BIT | |
| 75 | ||
| 76 | #define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \ | |
| 77 | EBC_BXCR_BS_16MB | \ | |
| 78 | EBC_BXCR_BU_RW | \ | |
| 79 | EBC_BXCR_BW_8BIT | |
| 80 | ||
| 81 | /* | |
| 82 | * Large Flash and SRAM | |
| 83 | * BU Value | |
| 84 | * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 | |
| 85 | * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 | |
| 86 | * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 | |
| 87 | */ | |
| 88 | #define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \ | |
| 89 | EBC_BXAP_TWT_ENCODE(7) | \ | |
| 90 | EBC_BXAP_BCE_DISABLE | \ | |
| 91 | EBC_BXAP_BCT_2TRANS | \ | |
| 92 | EBC_BXAP_CSN_ENCODE(0) | \ | |
| 93 | EBC_BXAP_OEN_ENCODE(0) | \ | |
| 94 | EBC_BXAP_WBN_ENCODE(0) | \ | |
| 95 | EBC_BXAP_WBF_ENCODE(0) | \ | |
| 96 | EBC_BXAP_TH_ENCODE(0) | \ | |
| 97 | EBC_BXAP_RE_DISABLED | \ | |
| 98 | EBC_BXAP_SOR_DELAYED | \ | |
| 99 | EBC_BXAP_BEM_WRITEONLY | \ | |
| 100 | EBC_BXAP_PEN_DISABLED | |
| 101 | ||
| 102 | #define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ | |
| 103 | EBC_BXCR_BS_16MB | \ | |
| 104 | EBC_BXCR_BU_RW | \ | |
| 105 | EBC_BXCR_BW_16BIT | |
| 106 | ||
| 107 | #define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \ | |
| 108 | EBC_BXCR_BS_16MB | \ | |
| 109 | EBC_BXCR_BU_RW | \ | |
| 110 | EBC_BXCR_BW_16BIT | |
| 111 | ||
| 112 | /* | |
| 113 | * FPGA | |
| 114 | * BU value : | |
| 115 | * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 | |
| 116 | * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000 | |
| 117 | */ | |
| 118 | #define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \ | |
| 119 | EBC_BXAP_TWT_ENCODE(11) | \ | |
| 120 | EBC_BXAP_BCE_DISABLE | \ | |
| 121 | EBC_BXAP_BCT_2TRANS | \ | |
| 122 | EBC_BXAP_CSN_ENCODE(10) | \ | |
| 123 | EBC_BXAP_OEN_ENCODE(1) | \ | |
| 124 | EBC_BXAP_WBN_ENCODE(1) | \ | |
| 125 | EBC_BXAP_WBF_ENCODE(1) | \ | |
| 126 | EBC_BXAP_TH_ENCODE(1) | \ | |
| 127 | EBC_BXAP_RE_DISABLED | \ | |
| 128 | EBC_BXAP_SOR_DELAYED | \ | |
| 129 | EBC_BXAP_BEM_RW | \ | |
| 130 | EBC_BXAP_PEN_DISABLED | |
| 131 | ||
| 132 | #define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \ | |
| 133 | EBC_BXCR_BS_1MB | \ | |
| 134 | EBC_BXCR_BU_RW | \ | |
| 135 | EBC_BXCR_BW_16BIT | |
| 136 | ||
| 137 | unsigned long mfr; | |
| 138 | /* | |
| 139 | * Define Variables for EBC initialization depending on BOOTSTRAP option | |
| 140 | */ | |
| 141 | unsigned long sdr0_pinstp, sdr0_sdstp1 ; | |
| 142 | unsigned long bootstrap_settings, ebc_data_width, boot_selection; | |
| 143 | int computed_boot_device = BOOT_DEVICE_UNKNOWN; | |
| 144 | ||
| 145 | /*-------------------------------------------------------------------+ | |
| 146 | | Initialize EBC CONFIG - | |
| 147 | | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC | |
| 148 | | default value : | |
| 149 | | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | |
| 150 | | | |
| 151 | +-------------------------------------------------------------------*/ | |
| d1c3b275 | 152 | mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | |
| 6c5879f3 MB |
153 | EBC_CFG_PTD_ENABLE | |
| 154 | EBC_CFG_RTC_16PERCLK | | |
| 155 | EBC_CFG_ATC_PREVIOUS | | |
| 156 | EBC_CFG_DTC_PREVIOUS | | |
| 157 | EBC_CFG_CTC_PREVIOUS | | |
| 158 | EBC_CFG_OEO_PREVIOUS | | |
| 159 | EBC_CFG_EMC_DEFAULT | | |
| 160 | EBC_CFG_PME_DISABLE | | |
| 161 | EBC_CFG_PR_16); | |
| 162 | ||
| 163 | /*-------------------------------------------------------------------+ | |
| 164 | | | |
| 165 | | PART 1 : Initialize EBC Bank 1 | |
| 166 | | ============================== | |
| 167 | | Bank1 is always associated to the EPLD. | |
| 168 | | It has to be initialized prior to other banks settings computation | |
| 169 | | since some board registers values may be needed to determine the | |
| 170 | | boot type | |
| 171 | | | |
| 172 | +-------------------------------------------------------------------*/ | |
| d1c3b275 SR |
173 | mtebc(PB1AP, EBC_BXAP_FPGA); |
| 174 | mtebc(PB1CR, EBC_BXCR_FPGA_CS1); | |
| 6c5879f3 MB |
175 | |
| 176 | /*-------------------------------------------------------------------+ | |
| 177 | | | |
| 178 | | PART 2 : Determine which boot device was selected | |
| 179 | | ================================================= | |
| 180 | | | |
| 181 | | Read Pin Strap Register in PPC440SPe | |
| 182 | | Result can either be : | |
| 183 | | - Boot strap = boot from EBC 8bits => Small Flash | |
| 184 | | - Boot strap = boot from PCI | |
| 185 | | - Boot strap = IIC | |
| 186 | | In case of boot from IIC, read Serial Device Strap Register1 | |
| 187 | | | |
| 188 | | Result can either be : | |
| 189 | | - Boot from EBC - EBC Bus Width = 8bits => Small Flash | |
| 190 | | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM | |
| 191 | | - Boot from PCI | |
| 192 | | | |
| 193 | +-------------------------------------------------------------------*/ | |
| 194 | /* Read Pin Strap Register in PPC440SP */ | |
| 2f5df473 | 195 | mfsdr(SDR0_PINSTP, sdr0_pinstp); |
| 6c5879f3 MB |
196 | bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK; |
| 197 | ||
| 198 | switch (bootstrap_settings) { | |
| 199 | case SDR0_PINSTP_BOOTSTRAP_SETTINGS0: | |
| 200 | /* | |
| 201 | * Strapping Option A | |
| 202 | * Boot from EBC - 8 bits , Small Flash | |
| 203 | */ | |
| 204 | computed_boot_device = BOOT_FROM_SMALL_FLASH; | |
| 205 | break; | |
| 206 | case SDR0_PINSTP_BOOTSTRAP_SETTINGS1: | |
| 207 | /* | |
| 208 | * Strappping Option B | |
| 209 | * Boot from PCI | |
| 210 | */ | |
| 211 | computed_boot_device = BOOT_FROM_PCI; | |
| 212 | break; | |
| 213 | case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN: | |
| 214 | case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN: | |
| 215 | /* | |
| 216 | * Strapping Option C or D | |
| 217 | * Boot Settings in IIC EEprom address 0x50 or 0x54 | |
| 218 | * Read Serial Device Strap Register1 in PPC440SPe | |
| 219 | */ | |
| 2f5df473 | 220 | mfsdr(SDR0_SDSTP1, sdr0_sdstp1); |
| 6c5879f3 MB |
221 | boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK; |
| 222 | ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK; | |
| 223 | ||
| 224 | switch (boot_selection) { | |
| 225 | case SDR0_SDSTP1_ERPN_EBC: | |
| 226 | switch (ebc_data_width) { | |
| 227 | case SDR0_SDSTP1_EBCW_16_BITS: | |
| 228 | computed_boot_device = | |
| 229 | BOOT_FROM_LARGE_FLASH_OR_SRAM; | |
| 230 | break; | |
| 231 | case SDR0_SDSTP1_EBCW_8_BITS : | |
| 232 | computed_boot_device = BOOT_FROM_SMALL_FLASH; | |
| 233 | break; | |
| 234 | } | |
| 235 | break; | |
| 236 | ||
| 237 | case SDR0_SDSTP1_ERPN_PCI: | |
| 238 | computed_boot_device = BOOT_FROM_PCI; | |
| 239 | break; | |
| 240 | default: | |
| 241 | /* should not occure */ | |
| 242 | computed_boot_device = BOOT_DEVICE_UNKNOWN; | |
| 243 | } | |
| 244 | break; | |
| 245 | default: | |
| 246 | /* should not be */ | |
| 247 | computed_boot_device = BOOT_DEVICE_UNKNOWN; | |
| 248 | break; | |
| 249 | } | |
| 250 | ||
| 251 | /*-------------------------------------------------------------------+ | |
| 252 | | | |
| 253 | | PART 3 : Compute EBC settings depending on selected boot device | |
| 254 | | ====== ====================================================== | |
| 255 | | | |
| 256 | | Resulting EBC init will be among following configurations : | |
| 257 | | | |
| 258 | | - Boot from EBC 8bits => boot from Small Flash selected | |
| 259 | | EBC-CS0 = Small Flash | |
| 260 | | EBC-CS2 = Large Flash and SRAM | |
| 261 | | | |
| 262 | | - Boot from EBC 16bits => boot from Large Flash or SRAM | |
| 263 | | EBC-CS0 = Large Flash or SRAM | |
| 264 | | EBC-CS2 = Small Flash | |
| 265 | | | |
| 266 | | - Boot from PCI | |
| 267 | | EBC-CS0 = not initialized to avoid address contention | |
| 268 | | EBC-CS2 = same as boot from Small Flash selected | |
| 269 | | | |
| 270 | +-------------------------------------------------------------------*/ | |
| 271 | unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0; | |
| 272 | unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0; | |
| 273 | ||
| 274 | switch (computed_boot_device) { | |
| 275 | /*-------------------------------------------------------------------*/ | |
| 276 | case BOOT_FROM_PCI: | |
| 277 | /*-------------------------------------------------------------------*/ | |
| 278 | /* | |
| 279 | * By Default CS2 is affected to LARGE Flash | |
| 280 | * do not initialize SMALL FLASH to avoid address contention | |
| 281 | * Large Flash | |
| 282 | */ | |
| 283 | ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; | |
| 284 | ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; | |
| 285 | break; | |
| 286 | ||
| 287 | /*-------------------------------------------------------------------*/ | |
| 288 | case BOOT_FROM_SMALL_FLASH: | |
| 289 | /*-------------------------------------------------------------------*/ | |
| 290 | ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH; | |
| 291 | ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0; | |
| 292 | ||
| 293 | /* | |
| 294 | * Large Flash or SRAM | |
| 295 | */ | |
| 296 | /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */ | |
| 297 | ebc0_cs2_bxap_value = 0x048ff240; | |
| 298 | ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; | |
| 299 | break; | |
| 300 | ||
| 301 | /*-------------------------------------------------------------------*/ | |
| 302 | case BOOT_FROM_LARGE_FLASH_OR_SRAM: | |
| 303 | /*-------------------------------------------------------------------*/ | |
| 304 | ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH; | |
| 305 | ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0; | |
| 306 | ||
| 307 | /* Small flash */ | |
| 308 | ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH; | |
| 309 | ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2; | |
| 310 | break; | |
| 311 | ||
| 312 | /*-------------------------------------------------------------------*/ | |
| 313 | default: | |
| 314 | /*-------------------------------------------------------------------*/ | |
| 315 | /* BOOT_DEVICE_UNKNOWN */ | |
| 316 | break; | |
| 317 | } | |
| 318 | ||
| d1c3b275 SR |
319 | mtebc(PB0AP, ebc0_cs0_bxap_value); |
| 320 | mtebc(PB0CR, ebc0_cs0_bxcr_value); | |
| 321 | mtebc(PB2AP, ebc0_cs2_bxap_value); | |
| 322 | mtebc(PB2CR, ebc0_cs2_bxcr_value); | |
| 6c5879f3 MB |
323 | |
| 324 | /*--------------------------------------------------------------------+ | |
| 325 | | Interrupt controller setup for the AMCC 440SPe Evaluation board. | |
| 326 | +--------------------------------------------------------------------+ | |
| 327 | +---------------------------------------------------------------------+ | |
| 328 | |Interrupt| Source | Pol. | Sensi.| Crit. | | |
| 329 | +---------+-----------------------------------+-------+-------+-------+ | |
| 330 | | IRQ 00 | UART0 | High | Level | Non | | |
| 331 | | IRQ 01 | UART1 | High | Level | Non | | |
| 332 | | IRQ 02 | IIC0 | High | Level | Non | | |
| 333 | | IRQ 03 | IIC1 | High | Level | Non | | |
| 334 | | IRQ 04 | PCI0X0 MSG IN | High | Level | Non | | |
| 335 | | IRQ 05 | PCI0X0 CMD Write | High | Level | Non | | |
| 336 | | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | | |
| 337 | | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | | |
| 338 | | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | | |
| 339 | | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | | |
| 340 | | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | | |
| 341 | | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | | |
| 342 | | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | | |
| 343 | | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | | |
| 344 | | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | | |
| 345 | | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | | |
| 346 | | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | | |
| 347 | | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | | |
| 348 | | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | | |
| 349 | | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | | |
| 350 | | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | | |
| 351 | | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | | |
| 352 | | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | | |
| 353 | | IRQ 23 | I2O Inbound Doorbell | High | Level | Non | | |
| 354 | | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | | |
| 355 | | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | | |
| 356 | | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | | |
| 357 | | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | | |
| 358 | | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | | |
| 359 | | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | | |
| 360 | | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | | |
| 361 | | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | | |
| 362 | |---------------------------------------------------------------------- | |
| 363 | | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | | |
| 364 | | IRQ 33 | MAL Serr | High | Level | Non | | |
| 365 | | IRQ 34 | MAL Txde | High | Level | Non | | |
| 366 | | IRQ 35 | MAL Rxde | High | Level | Non | | |
| 367 | | IRQ 36 | DMC CE or DMC UE | High | Level | Non | | |
| 368 | | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | | |
| 369 | | IRQ 38 | MAL TX EOB | High | Level | Non | | |
| 370 | | IRQ 39 | MAL RX EOB | High | Level | Non | | |
| 371 | | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | | |
| 372 | | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | | |
| 373 | | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | | |
| 374 | | IRQ 43 | L2 Cache | Risin | Edge | Non | | |
| 375 | | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | | |
| 376 | | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | | |
| 377 | | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | | |
| 378 | | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | | |
| 379 | | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | | |
| 380 | | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | | |
| 381 | | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | | |
| 382 | | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | | |
| 383 | | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | | |
| 384 | | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | | |
| 385 | | IRQ 54 | DMA Error | High | Level | Non | | |
| 386 | | IRQ 55 | DMA I2O Error | High | Level | Non | | |
| 387 | | IRQ 56 | Serial ROM | High | Level | Non | | |
| 388 | | IRQ 57 | PCIX0 Error | High | Edge | Non | | |
| 389 | | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | | |
| 390 | | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | | |
| 391 | | IRQ 60 | EMAC0 Interrupt | High | Level | Non | | |
| 392 | | IRQ 61 | EMAC0 Wake-up | High | Level | Non | | |
| 393 | | IRQ 62 | Reserved | High | Level | Non | | |
| 394 | | IRQ 63 | XOR | High | Level | Non | | |
| 395 | |---------------------------------------------------------------------- | |
| 396 | | IRQ 64 | PE0 AL | High | Level | Non | | |
| 397 | | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | | |
| 398 | | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | | |
| 399 | | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | | |
| 400 | | IRQ 68 | PE0 TCR | High | Level | Non | | |
| 401 | | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | | |
| 402 | | IRQ 70 | PE0 DCR Error | High | Level | Non | | |
| 403 | | IRQ 71 | Reserved | N/A | N/A | Non | | |
| 404 | | IRQ 72 | PE1 AL | High | Level | Non | | |
| 405 | | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | | |
| 406 | | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | | |
| 407 | | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | | |
| 408 | | IRQ 76 | PE1 TCR | High | Level | Non | | |
| 409 | | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | | |
| 410 | | IRQ 78 | PE1 DCR Error | High | Level | Non | | |
| 411 | | IRQ 79 | Reserved | N/A | N/A | Non | | |
| 412 | | IRQ 80 | PE2 AL | High | Level | Non | | |
| 413 | | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | | |
| 414 | | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | | |
| 415 | | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | | |
| 416 | | IRQ 84 | PE2 TCR | High | Level | Non | | |
| 417 | | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | | |
| 418 | | IRQ 86 | PE2 DCR Error | High | Level | Non | | |
| 419 | | IRQ 87 | Reserved | N/A | N/A | Non | | |
| 420 | | IRQ 88 | External IRQ(5) | Progr | Progr | Non | | |
| 421 | | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | | |
| 422 | | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | | |
| 423 | | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | | |
| 424 | | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | | |
| 425 | | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | | |
| 426 | | IRQ 94 | Reserved | N/A | N/A | Non | | |
| 427 | | IRQ 95 | Reserved | N/A | N/A | Non | | |
| 428 | |--------------------------------------------------------------------- | |
| 429 | | IRQ 96 | PE0 INTA | High | Level | Non | | |
| 430 | | IRQ 97 | PE0 INTB | High | Level | Non | | |
| 431 | | IRQ 98 | PE0 INTC | High | Level | Non | | |
| 432 | | IRQ 99 | PE0 INTD | High | Level | Non | | |
| 433 | | IRQ 100 | PE1 INTA | High | Level | Non | | |
| 434 | | IRQ 101 | PE1 INTB | High | Level | Non | | |
| 435 | | IRQ 102 | PE1 INTC | High | Level | Non | | |
| 436 | | IRQ 103 | PE1 INTD | High | Level | Non | | |
| 437 | | IRQ 104 | PE2 INTA | High | Level | Non | | |
| 438 | | IRQ 105 | PE2 INTB | High | Level | Non | | |
| 439 | | IRQ 106 | PE2 INTC | High | Level | Non | | |
| 440 | | IRQ 107 | PE2 INTD | Risin | Edge | Non | | |
| 441 | | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | | |
| 442 | | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | | |
| 443 | | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | | |
| 444 | | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | | |
| 445 | | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | | |
| 446 | | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | | |
| 447 | | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | | |
| 448 | | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | | |
| 449 | | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | | |
| 450 | | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | | |
| 451 | | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | | |
| 452 | | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | | |
| 453 | | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | | |
| 454 | | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | | |
| 455 | | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | | |
| 456 | | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | | |
| 457 | | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | | |
| 458 | | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | | |
| 459 | | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | | |
| 460 | | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | | |
| 461 | +---------+-----------------------------------+-------+-------+------*/ | |
| 462 | /*--------------------------------------------------------------------+ | |
| 463 | | Put UICs in PowerPC440SPemode. | |
| 464 | | Initialise UIC registers. Clear all interrupts. Disable all | |
| 465 | | interrupts. | |
| 466 | | Set critical interrupt values. Set interrupt polarities. Set | |
| 467 | | interrupt trigger levels. Make bit 0 High priority. Clear all | |
| 468 | | interrupts again. | |
| 469 | +-------------------------------------------------------------------*/ | |
| 952e7760 SR |
470 | mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ |
| 471 | mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ | |
| 472 | mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical | |
| 6c5879f3 | 473 | * interrupts */ |
| 952e7760 SR |
474 | mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ |
| 475 | mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ | |
| 476 | mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest | |
| 6c5879f3 | 477 | * priority */ |
| 952e7760 SR |
478 | mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */ |
| 479 | mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */ | |
| 6c5879f3 | 480 | |
| 952e7760 SR |
481 | mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ |
| 482 | mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ | |
| 483 | mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical | |
| 6c5879f3 | 484 | * interrupts */ |
| 952e7760 SR |
485 | mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ |
| 486 | mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ | |
| 487 | mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest | |
| 6c5879f3 | 488 | * priority */ |
| 952e7760 SR |
489 | mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ |
| 490 | mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ | |
| 6c5879f3 | 491 | |
| 952e7760 SR |
492 | mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ |
| 493 | mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ | |
| 494 | mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical | |
| 6c5879f3 | 495 | * interrupts */ |
| 952e7760 SR |
496 | mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ |
| 497 | mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */ | |
| 498 | mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest | |
| 6c5879f3 | 499 | * priority */ |
| 952e7760 SR |
500 | mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ |
| 501 | mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ | |
| 6c5879f3 | 502 | |
| 952e7760 SR |
503 | mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ |
| 504 | mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted | |
| 6c5879f3 | 505 | * cascade to be checked */ |
| 952e7760 | 506 | mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical |
| 6c5879f3 | 507 | * interrupts */ |
| 952e7760 SR |
508 | mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ |
| 509 | mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ | |
| 510 | mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest | |
| 6c5879f3 | 511 | * priority */ |
| 952e7760 SR |
512 | mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ |
| 513 | mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ | |
| 6c5879f3 | 514 | |
| d1c3b275 | 515 | mfsdr(SDR0_MFR, mfr); |
| a27044b1 | 516 | mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ |
| d1c3b275 | 517 | mtsdr(SDR0_MFR, mfr); |
| a27044b1 | 518 | |
| 6c5879f3 MB |
519 | fpga_init(); |
| 520 | ||
| 521 | return 0; | |
| 522 | } | |
| 523 | ||
| 524 | int checkboard (void) | |
| 525 | { | |
| f0c0b3a9 WD |
526 | char buf[64]; |
| 527 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
| fe84b48a MB |
528 | |
| 529 | printf("Board: Yucca - AMCC 440SPe Evaluation Board"); | |
| f0c0b3a9 | 530 | if (i > 0) { |
| fe84b48a | 531 | puts(", serial# "); |
| f0c0b3a9 | 532 | puts(buf); |
| fe84b48a MB |
533 | } |
| 534 | putc('\n'); | |
| 535 | ||
| 6c5879f3 MB |
536 | return 0; |
| 537 | } | |
| 538 | ||
| df3f1742 | 539 | /* |
| a47a12be | 540 | * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with |
| df3f1742 SR |
541 | * board specific values. |
| 542 | */ | |
| 543 | static int ppc440spe_rev_a(void) | |
| 544 | { | |
| 545 | if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA)) | |
| 546 | return 1; | |
| 547 | else | |
| 548 | return 0; | |
| 549 | } | |
| 550 | ||
| 551 | u32 ddr_wrdtr(u32 default_val) { | |
| 552 | /* | |
| 553 | * Yucca boards with 440SPe rev. A need a slightly different setup | |
| 554 | * for the MCIF0_WRDTR register. | |
| 555 | */ | |
| 556 | if (ppc440spe_rev_a()) | |
| 557 | return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV); | |
| 558 | ||
| 559 | return default_val; | |
| 560 | } | |
| 561 | ||
| 562 | u32 ddr_clktr(u32 default_val) { | |
| 563 | /* | |
| 564 | * Yucca boards with 440SPe rev. A need a slightly different setup | |
| 565 | * for the MCIF0_CLKTR register. | |
| 566 | */ | |
| 567 | if (ppc440spe_rev_a()) | |
| 568 | return (SDRAM_CLKTR_CLKP_180_DEG_ADV); | |
| 569 | ||
| 570 | return default_val; | |
| 571 | } | |
| 572 | ||
| 692519b1 | 573 | #if defined(CONFIG_PCI) |
| b0b86746 | 574 | int board_pcie_card_present(int port) |
| 692519b1 RJ |
575 | { |
| 576 | u16 reg; | |
| 577 | ||
| 578 | reg = in_be16((u16 *)FPGA_REG1C); | |
| 579 | switch(port) { | |
| 580 | case 0: | |
| 581 | return !(reg & FPGA_REG1C_PE0_PRSNT); | |
| 582 | case 1: | |
| 583 | return !(reg & FPGA_REG1C_PE1_PRSNT); | |
| 584 | case 2: | |
| 585 | return !(reg & FPGA_REG1C_PE2_PRSNT); | |
| 586 | default: | |
| 587 | return 0; | |
| 588 | } | |
| 589 | } | |
| 590 | ||
| 2b393b0f SR |
591 | /* |
| 592 | * For the given slot, set endpoint mode, send power to the slot, | |
| b0b86746 | 593 | * turn on the green LED and turn off the yellow LED, enable the |
| 64917ca3 | 594 | * clock. In endpoint mode reset bit is read only. |
| 2b393b0f | 595 | */ |
| b0b86746 | 596 | void board_pcie_setup_port(int port, int rootpoint) |
| 2b393b0f | 597 | { |
| b0b86746 SR |
598 | u16 power, clock, green_led, yellow_led, |
| 599 | reset_off, rp, ep; | |
| 2b393b0f | 600 | |
| b0b86746 | 601 | switch (port) { |
| 2b393b0f | 602 | case 0: |
| b0b86746 SR |
603 | rp = FPGA_REG1C_PE0_ROOTPOINT; |
| 604 | ep = 0; | |
| 2b393b0f SR |
605 | break; |
| 606 | case 1: | |
| b0b86746 SR |
607 | rp = 0; |
| 608 | ep = FPGA_REG1C_PE1_ENDPOINT; | |
| 2b393b0f SR |
609 | break; |
| 610 | case 2: | |
| b0b86746 SR |
611 | rp = 0; |
| 612 | ep = FPGA_REG1C_PE2_ENDPOINT; | |
| 2b393b0f SR |
613 | break; |
| 614 | ||
| 615 | default: | |
| 616 | return; | |
| 617 | } | |
| 618 | ||
| b0b86746 SR |
619 | power = FPGA_REG1A_PWRON_ENCODE(port); |
| 620 | green_led = FPGA_REG1A_GLED_ENCODE(port); | |
| 621 | clock = FPGA_REG1A_REFCLK_ENCODE(port); | |
| 622 | yellow_led = FPGA_REG1A_YLED_ENCODE(port); | |
| 623 | reset_off = FPGA_REG1C_PERST_ENCODE(port); | |
| 2b393b0f | 624 | |
| b0b86746 SR |
625 | out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) & |
| 626 | (yellow_led | in_be16((u16 *)FPGA_REG1A))); | |
| 2b393b0f | 627 | |
| b0b86746 SR |
628 | out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) & |
| 629 | (rp | in_be16((u16 *)FPGA_REG1C))); | |
| 692519b1 | 630 | |
| b0b86746 SR |
631 | if (rootpoint) { |
| 632 | /* | |
| 633 | * Leave device in reset for a while after powering on the | |
| 634 | * slot to give it a chance to initialize. | |
| 635 | */ | |
| 636 | udelay(250 * 1000); | |
| 692519b1 | 637 | |
| b0b86746 SR |
638 | out_be16((u16 *)FPGA_REG1C, |
| 639 | reset_off | in_be16((u16 *)FPGA_REG1C)); | |
| 692519b1 RJ |
640 | } |
| 641 | } | |
| 6c5879f3 MB |
642 | #endif /* defined(CONFIG_PCI) */ |
| 643 | ||
| 644 | int misc_init_f (void) | |
| 645 | { | |
| 646 | uint reg; | |
| 6c5879f3 MB |
647 | |
| 648 | out16(FPGA_REG10, (in16(FPGA_REG10) & | |
| 649 | ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) | | |
| 650 | FPGA_REG10_10MHZ_ENABLE | | |
| 651 | FPGA_REG10_100MHZ_ENABLE | | |
| 652 | FPGA_REG10_GIGABIT_ENABLE | | |
| 653 | FPGA_REG10_FULL_DUPLEX ); | |
| 654 | ||
| 655 | udelay(10000); /* wait 10ms */ | |
| 656 | ||
| 657 | out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH)); | |
| 658 | ||
| 659 | /* minimal init for PCIe */ | |
| 660 | /* pci express 0 Endpoint Mode */ | |
| d9056b79 | 661 | mfsdr(SDRN_PESDR_DLPSET(0), reg); |
| 6c5879f3 | 662 | reg &= (~0x00400000); |
| d9056b79 | 663 | mtsdr(SDRN_PESDR_DLPSET(0), reg); |
| 6c5879f3 | 664 | /* pci express 1 Rootpoint Mode */ |
| d9056b79 | 665 | mfsdr(SDRN_PESDR_DLPSET(1), reg); |
| 6c5879f3 | 666 | reg |= 0x00400000; |
| d9056b79 | 667 | mtsdr(SDRN_PESDR_DLPSET(1), reg); |
| 6c5879f3 | 668 | /* pci express 2 Rootpoint Mode */ |
| d9056b79 | 669 | mfsdr(SDRN_PESDR_DLPSET(2), reg); |
| 6c5879f3 | 670 | reg |= 0x00400000; |
| d9056b79 | 671 | mtsdr(SDRN_PESDR_DLPSET(2), reg); |
| 6c5879f3 MB |
672 | |
| 673 | out16(FPGA_REG1C,(in16 (FPGA_REG1C) & | |
| 674 | ~FPGA_REG1C_PE0_ROOTPOINT & | |
| 675 | ~FPGA_REG1C_PE1_ENDPOINT & | |
| 676 | ~FPGA_REG1C_PE2_ENDPOINT)); | |
| 677 | ||
| 6c5879f3 MB |
678 | return 0; |
| 679 | } | |
| 680 | ||
| 681 | void fpga_init(void) | |
| 682 | { | |
| 683 | /* | |
| 684 | * by default sdram access is disabled by fpga | |
| 685 | */ | |
| 686 | out16(FPGA_REG10, (in16 (FPGA_REG10) | | |
| 687 | FPGA_REG10_SDRAM_ENABLE | | |
| 688 | FPGA_REG10_ENABLE_DISPLAY )); | |
| 689 | ||
| 690 | return; | |
| 691 | } | |
| 692 | ||
| 6c5879f3 MB |
693 | /*---------------------------------------------------------------------------+ |
| 694 | | onboard_pci_arbiter_selected => from EPLD | |
| 695 | +---------------------------------------------------------------------------*/ | |
| 696 | int onboard_pci_arbiter_selected(int core_pci) | |
| 697 | { | |
| 698 | #if 0 | |
| 699 | unsigned long onboard_pci_arbiter_sel; | |
| 700 | ||
| 701 | onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK; | |
| 702 | ||
| 703 | if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL) | |
| 704 | return (BOARD_OPTION_SELECTED); | |
| 705 | else | |
| 706 | #endif | |
| 707 | return (BOARD_OPTION_NOT_SELECTED); | |
| 708 | } | |
| 10efa024 BW |
709 | |
| 710 | int board_eth_init(bd_t *bis) | |
| 711 | { | |
| cef0efaf | 712 | cpu_eth_init(bis); |
| 10efa024 BW |
713 | return pci_eth_init(bis); |
| 714 | } |