[people/ms/u-boot.git] / board / amcc / yucca / yucca.h

/*
 * (C) Copyright 2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __YUCCA_H_
#define __YUCCA_H_

#ifdef __cplusplus
extern "C" {
#endif

/*----------------------------------------------------------------------------+
| Defines
+----------------------------------------------------------------------------*/

#define TMR_FREQ_EXT		25000000
#define BOARD_UART_CLOCK	11059200

#define BOARD_OPTION_SELECTED		1
#define BOARD_OPTION_NOT_SELECTED	0

#define ENGINEERING_CLOCK_CHECKING "clk_chk"
#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"

#define ENGINEERING_CLOCK_CHECKING_DATA	1
#define ENGINEERING_EXTERNAL_CLOCK_DATA	2

/* ethernet definition */
#define MAX_ENETMODE_PARM	3
#define ENETMODE_NEG		0
#define ENETMODE_SPEED		1
#define ENETMODE_DUPLEX		2

#define ENETMODE_AUTONEG	0
#define ENETMODE_NO_AUTONEG	1
#define ENETMODE_10		2
#define ENETMODE_100		3
#define ENETMODE_1000		4
#define ENETMODE_HALF		5
#define ENETMODE_FULL		6

#define NUM_TLB_ENTRIES          64

/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */
#define MICRON_SPD_JEDEC_ID 0x2c

/*----------------------------------------------------------------------------+
| TLB specific defines.
+----------------------------------------------------------------------------*/
#define TLB_256MB_ALIGN_MASK	0xF0000000
#define TLB_16MB_ALIGN_MASK	0xFF000000
#define TLB_1MB_ALIGN_MASK	0xFFF00000
#define TLB_256KB_ALIGN_MASK	0xFFFC0000
#define TLB_64KB_ALIGN_MASK	0xFFFF0000
#define TLB_16KB_ALIGN_MASK	0xFFFFC000
#define TLB_4KB_ALIGN_MASK	0xFFFFF000
#define TLB_1KB_ALIGN_MASK	0xFFFFFC00
#define TLB_256MB_SIZE		0x10000000
#define TLB_16MB_SIZE		0x01000000
#define TLB_1MB_SIZE		0x00100000
#define TLB_256KB_SIZE		0x00040000
#define TLB_64KB_SIZE		0x00010000
#define TLB_16KB_SIZE		0x00004000
#define TLB_4KB_SIZE		0x00001000
#define TLB_1KB_SIZE		0x00000400

#define TLB_WORD0_EPN_MASK	0xFFFFFC00
#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_V_MASK	0x00000200
#define TLB_WORD0_V_ENABLE	0x00000200
#define TLB_WORD0_V_DISABLE	0x00000000
#define TLB_WORD0_TS_MASK	0x00000100
#define TLB_WORD0_TS_1		0x00000100
#define TLB_WORD0_TS_0		0x00000000
#define TLB_WORD0_SIZE_MASK	0x000000F0
#define TLB_WORD0_SIZE_1KB	0x00000000
#define TLB_WORD0_SIZE_4KB	0x00000010
#define TLB_WORD0_SIZE_16KB	0x00000020
#define TLB_WORD0_SIZE_64KB	0x00000030
#define TLB_WORD0_SIZE_256KB	0x00000040
#define TLB_WORD0_SIZE_1MB	0x00000050
#define TLB_WORD0_SIZE_16MB	0x00000070
#define TLB_WORD0_SIZE_256MB	0x00000090
#define TLB_WORD0_TPAR_MASK	0x0000000F
#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)

#define TLB_WORD1_RPN_MASK	0xFFFFFC00
#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_PAR1_MASK	0x00000300
#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
#define TLB_WORD1_PAR1_0	0x00000000
#define TLB_WORD1_PAR1_1	0x00000100
#define TLB_WORD1_PAR1_2	0x00000200
#define TLB_WORD1_PAR1_3	0x00000300
#define TLB_WORD1_ERPN_MASK	0x0000000F
#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)

#define TLB_WORD2_PAR2_MASK	0xC0000000
#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
#define TLB_WORD2_PAR2_0	0x00000000
#define TLB_WORD2_PAR2_1	0x40000000
#define TLB_WORD2_PAR2_2	0x80000000
#define TLB_WORD2_PAR2_3	0xC0000000
#define TLB_WORD2_U0_MASK	0x00008000
#define TLB_WORD2_U0_ENABLE	0x00008000
#define TLB_WORD2_U0_DISABLE	0x00000000
#define TLB_WORD2_U1_MASK	0x00004000
#define TLB_WORD2_U1_ENABLE	0x00004000
#define TLB_WORD2_U1_DISABLE	0x00000000
#define TLB_WORD2_U2_MASK	0x00002000
#define TLB_WORD2_U2_ENABLE	0x00002000
#define TLB_WORD2_U2_DISABLE	0x00000000
#define TLB_WORD2_U3_MASK	0x00001000
#define TLB_WORD2_U3_ENABLE	0x00001000
#define TLB_WORD2_U3_DISABLE	0x00000000
#define TLB_WORD2_W_MASK	0x00000800
#define TLB_WORD2_W_ENABLE	0x00000800
#define TLB_WORD2_W_DISABLE	0x00000000
#define TLB_WORD2_I_MASK	0x00000400
#define TLB_WORD2_I_ENABLE	0x00000400
#define TLB_WORD2_I_DISABLE	0x00000000
#define TLB_WORD2_M_MASK	0x00000200
#define TLB_WORD2_M_ENABLE	0x00000200
#define TLB_WORD2_M_DISABLE	0x00000000
#define TLB_WORD2_G_MASK	0x00000100
#define TLB_WORD2_G_ENABLE	0x00000100
#define TLB_WORD2_G_DISABLE	0x00000000
#define TLB_WORD2_E_MASK	0x00000080
#define TLB_WORD2_E_ENABLE	0x00000080
#define TLB_WORD2_E_DISABLE	0x00000000
#define TLB_WORD2_UX_MASK	0x00000020
#define TLB_WORD2_UX_ENABLE	0x00000020
#define TLB_WORD2_UX_DISABLE	0x00000000
#define TLB_WORD2_UW_MASK	0x00000010
#define TLB_WORD2_UW_ENABLE	0x00000010
#define TLB_WORD2_UW_DISABLE	0x00000000
#define TLB_WORD2_UR_MASK	0x00000008
#define TLB_WORD2_UR_ENABLE	0x00000008
#define TLB_WORD2_UR_DISABLE	0x00000000
#define TLB_WORD2_SX_MASK	0x00000004
#define TLB_WORD2_SX_ENABLE	0x00000004
#define TLB_WORD2_SX_DISABLE	0x00000000
#define TLB_WORD2_SW_MASK	0x00000002
#define TLB_WORD2_SW_ENABLE	0x00000002
#define TLB_WORD2_SW_DISABLE	0x00000000
#define TLB_WORD2_SR_MASK	0x00000001
#define TLB_WORD2_SR_ENABLE	0x00000001
#define TLB_WORD2_SR_DISABLE	0x00000000

/*----------------------------------------------------------------------------+
| Board specific defines.
+----------------------------------------------------------------------------*/
#define NONCACHE_MEMORY_SIZE     (64*1024)
#define NONCACHE_AREA0_ENDOFFSET (64*1024)
#define NONCACHE_AREA1_ENDOFFSET (32*1024)

#define FLASH_SECTORSIZE	0x00010000

/* SDRAM MICRON */
#define SDRAM_MICRON		0x2C

#define SDRAM_TRUE		1
#define SDRAM_FALSE		0
#define SDRAM_DDR1		1
#define SDRAM_DDR2		2
#define SDRAM_NONE		0
#define MAXDIMMS		2		/* Changes le 12/01/05 pour 1.6 */
#define MAXRANKS		4		/* Changes le 12/01/05 pour 1.6 */
#define MAXBANKSPERDIMM		2
#define MAXRANKSPERDIMM		2
#define MAXBXCF			4		/* Changes le 12/01/05 pour 1.6 */
#define MAXSDRAMMEMORY		0xFFFFFFFF	/* 4GB */
#define ERROR_STR_LENGTH	256
#define MAX_SPD_BYTES		256		/* Max number of bytes on the DIMM's SPD EEPROM */

/*----------------------------------------------------------------------------+
| SDR Configuration registers
+----------------------------------------------------------------------------*/
/* Serial Device Strap Reg 0 */
#define sdr_pstrp0	0x0040

#define	SDR0_SDSTP1_EBC_ROM_BS_MASK	0x00000080 /* EBC Boot bus width Mask */
#define	SDR0_SDSTP1_EBC_ROM_BS_16BIT	0x00000080 /* EBC 16 Bits */
#define	SDR0_SDSTP1_EBC_ROM_BS_8BIT	0x00000000 /* EBC  8 Bits */

#define	SDR0_SDSTP1_BOOT_SEL_MASK	0x00080000 /* Boot device Selection Mask */
#define	SDR0_SDSTP1_BOOT_SEL_EBC	0x00000000 /* EBC */
#define	SDR0_SDSTP1_BOOT_SEL_PCI	0x00080000 /* PCI */

#define	SDR0_SDSTP1_EBC_SIZE_MASK	0x00000060 /* Boot rom size Mask */
#define	SDR0_SDSTP1_BOOT_SIZE_16MB	0x00000060 /* 16 MB */
#define	SDR0_SDSTP1_BOOT_SIZE_8MB	0x00000040 /*  8 MB */
#define	SDR0_SDSTP1_BOOT_SIZE_4MB	0x00000020 /*  4 MB */
#define	SDR0_SDSTP1_BOOT_SIZE_2MB	0x00000000 /*  2 MB */

/* Serial Device Enabled - Addr = 0xA8 */
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
/* Serial Device Enabled - Addr = 0xA4 */
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7

/* Pin Straps Reg */
#define SDR0_PSTRP0			0x0040
#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000  /* Strap Bits */

#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0	0x00000000  /* Default strap settings 0 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1	0x20000000  /* Default strap settings 1 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2	0x40000000  /* Default strap settings 2 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3	0x60000000  /* Default strap settings 3 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4	0x80000000  /* Default strap settings 4 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5	0xA0000000  /* Default strap settings 5 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6	0xC0000000  /* Default strap settings 6 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7	0xE0000000  /* Default strap settings 7 */

/* fpgareg - defines are in include/config/YUCCA.h */

#define SDR0_CUST0_ENET3_MASK		0x00000080
#define SDR0_CUST0_ENET3_COPPER		0x00000000
#define SDR0_CUST0_ENET3_FIBER		0x00000080
#define SDR0_CUST0_RGMII3_MASK		0x00000070
#define SDR0_CUST0_RGMII3_ENCODE(n)	((((unsigned long)(n))&0x7)<<4)
#define SDR0_CUST0_RGMII3_DECODE(n)	((((unsigned long)(n))>>4)&0x07)
#define SDR0_CUST0_RGMII3_DISAB		0x00000000
#define SDR0_CUST0_RGMII3_RTBI		0x00000040
#define SDR0_CUST0_RGMII3_RGMII		0x00000050
#define SDR0_CUST0_RGMII3_TBI		0x00000060
#define SDR0_CUST0_RGMII3_GMII		0x00000070
#define SDR0_CUST0_ENET2_MASK		0x00000008
#define SDR0_CUST0_ENET2_COPPER		0x00000000
#define SDR0_CUST0_ENET2_FIBER		0x00000008
#define SDR0_CUST0_RGMII2_MASK		0x00000007
#define SDR0_CUST0_RGMII2_ENCODE(n)	((((unsigned long)(n))&0x7)<<0)
#define SDR0_CUST0_RGMII2_DECODE(n)	((((unsigned long)(n))>>0)&0x07)
#define SDR0_CUST0_RGMII2_DISAB		0x00000000
#define SDR0_CUST0_RGMII2_RTBI		0x00000004
#define SDR0_CUST0_RGMII2_RGMII		0x00000005
#define SDR0_CUST0_RGMII2_TBI		0x00000006
#define SDR0_CUST0_RGMII2_GMII		0x00000007

#define ONE_MILLION			1000000
#define ONE_BILLION			1000000000

/*----------------------------------------------------------------------------+
|                               X
|                              XX
| XX  XXX   XXXXX   XX XXX    XXXXX
| XX  XX        X    XXX XX    XX
| XX  XX   XXXXXX    XX        XX
| XX  XX   X   XX    XX        XX XX
|  XXX XX  XXXXX X  XXXX        XXX
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
| Declare Configuration values
+----------------------------------------------------------------------------*/

typedef enum config_selection {
	CONFIG_NOT_SELECTED,
	CONFIG_SELECTED
} config_selection_t;

typedef enum config_list {
	UART2_IN_SERVICE_MODE,
	CPU_TRACE_MODE,
	UART1_CTS_RTS,
	CONFIG_NB
} config_list_t;

#define MAX_CONFIG_SELECT_NB			3

#define BOARD_INFO_UART2_IN_SERVICE_MODE	1
#define BOARD_INFO_CPU_TRACE_MODE		2
#define BOARD_INFO_UART1_CTS_RTS_MODE		4

void force_bup_config_selection(config_selection_t *confgi_select_P);
void update_config_selection_table(config_selection_t *config_select_P);
void display_config_selection(config_selection_t *config_select_P);

/*----------------------------------------------------------------------------+
|                     XX
|
|   XXXX    XX XXX   XXX     XXXX
|  XX        XX  XX   XX    XX  XX
|  XX  XXX   XX  XX   XX    XX  XX
|  XX  XX    XXXXX    XX    XX  XX
|   XXXX     XX      XXXX    XXXX
|           XXXX
|
|
|
| +------------------------------------------------------------------+
| |  GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
| +----------------------+------------------+-----+------------+-----+
| |                      |                  |     |            |     |
| | GPIO0_0              | PCIX0REQ2_N      | I/O |  TRCCLK    |     |
| | GPIO0_1              | PCIX0REQ3_N      | I/O |  TRCBS0    |     |
| | GPIO0_2              | PCIX0GNT2_N      | I/O |  TRCBS1    |     |
| | GPIO0_3              | PCIX0GNT3_N      | I/O |  TRCBS2    |     |
| | GPIO0_4              | PCIX1REQ2_N      | I/O |  TRCES0    |     |
| | GPIO0_5              | PCIX1REQ3_N      | I/O |  TRCES1    |     |
| | GPIO0_6              | PCIX1GNT2_N      | I/O |  TRCES2    | NA  |
| | GPIO0_7              | PCIX1GNT3_N      | I/O |  TRCES3    | NA  |
| | GPIO0_8              | PERREADY         |  I  |  TRCES4    | NA  |
| | GPIO0_9              | PERCS1_N         |  O  |  TRCTS0    | NA  |
| | GPIO0_10             | PERCS2_N         |  O  |  TRCTS1    | NA  |
| | GPIO0_11             | IRQ0             |  I  |  TRCTS2    | NA  |
| | GPIO0_12             | IRQ1             |  I  |  TRCTS3    | NA  |
| | GPIO0_13             | IRQ2             |  I  |  TRCTS4    | NA  |
| | GPIO0_14             | IRQ3             |  I  |  TRCTS5    | NA  |
| | GPIO0_15             | IRQ4             |  I  |  TRCTS6    | NA  |
| | GPIO0_16             | IRQ5             |  I  |  UART2RX   |  I  |
| | GPIO0_17             | PERBE0_N         |  O  |  UART2TX   |  O  |
| | GPIO0_18             | PCI0GNT0_N       | I/O |  NA        | NA  |
| | GPIO0_19             | PCI0GNT1_N       | I/O |  NA        | NA  |
| | GPIO0_20             | PCI0REQ0_N       | I/O |  NA        | NA  |
| | GPIO0_21             | PCI0REQ1_N       | I/O |  NA        | NA  |
| | GPIO0_22             | PCI1GNT0_N       | I/O |  NA        | NA  |
| | GPIO0_23             | PCI1GNT1_N       | I/O |  NA        | NA  |
| | GPIO0_24             | PCI1REQ0_N       | I/O |  NA        | NA  |
| | GPIO0_25             | PCI1REQ1_N       | I/O |  NA        | NA  |
| | GPIO0_26             | PCI2GNT0_N       | I/O |  NA        | NA  |
| | GPIO0_27             | PCI2GNT1_N       | I/O |  NA        | NA  |
| | GPIO0_28             | PCI2REQ0_N       | I/O |  NA        | NA  |
| | GPIO0_29             | PCI2REQ1_N       | I/O |  NA        | NA  |
| | GPIO0_30             | UART1RX          |  I  |  NA        | NA  |
| | GPIO0_31             | UART1TX          |  O  |  NA        | NA  |
| |                      |                  |     |            |     |
| +----------------------+------------------+-----+------------+-----+
|
+----------------------------------------------------------------------------*/

unsigned long auto_calc_speed(void);
/*----------------------------------------------------------------------------+
| Prototypes
+----------------------------------------------------------------------------*/
void print_evb440spe_info(void);

int onboard_pci_arbiter_selected(int core_pci);

#ifdef __cplusplus
}
#endif
#endif /* __YUCCA_H_ */
Commit	Line	Data
6c5879f3 MB	1	/*
	2	* (C) Copyright 2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __YUCCA_H_
	25	#define __YUCCA_H_
	26
	27	#ifdef __cplusplus
	28	extern "C" {
	29	#endif
	30
	31	/*----------------------------------------------------------------------------+
	32	\| Defines
	33	+----------------------------------------------------------------------------*/
	34
	35	#define TMR_FREQ_EXT 25000000
	36	#define BOARD_UART_CLOCK 11059200
	37
	38	#define BOARD_OPTION_SELECTED 1
	39	#define BOARD_OPTION_NOT_SELECTED 0
	40
	41	#define ENGINEERING_CLOCK_CHECKING "clk_chk"
	42	#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
	43
	44	#define ENGINEERING_CLOCK_CHECKING_DATA 1
	45	#define ENGINEERING_EXTERNAL_CLOCK_DATA 2
	46
	47	/* ethernet definition */
	48	#define MAX_ENETMODE_PARM 3
	49	#define ENETMODE_NEG 0
	50	#define ENETMODE_SPEED 1
	51	#define ENETMODE_DUPLEX 2
	52
	53	#define ENETMODE_AUTONEG 0
	54	#define ENETMODE_NO_AUTONEG 1
	55	#define ENETMODE_10 2
	56	#define ENETMODE_100 3
	57	#define ENETMODE_1000 4
	58	#define ENETMODE_HALF 5
	59	#define ENETMODE_FULL 6
	60
	61	#define NUM_TLB_ENTRIES 64
	62
f5577aae SR	63	/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */
	64	#define MICRON_SPD_JEDEC_ID 0x2c
	65
6c5879f3 MB	66	/*----------------------------------------------------------------------------+
	67	\| TLB specific defines.
	68	+----------------------------------------------------------------------------*/
	69	#define TLB_256MB_ALIGN_MASK 0xF0000000
	70	#define TLB_16MB_ALIGN_MASK 0xFF000000
	71	#define TLB_1MB_ALIGN_MASK 0xFFF00000
	72	#define TLB_256KB_ALIGN_MASK 0xFFFC0000
	73	#define TLB_64KB_ALIGN_MASK 0xFFFF0000
	74	#define TLB_16KB_ALIGN_MASK 0xFFFFC000
	75	#define TLB_4KB_ALIGN_MASK 0xFFFFF000
	76	#define TLB_1KB_ALIGN_MASK 0xFFFFFC00
	77	#define TLB_256MB_SIZE 0x10000000
	78	#define TLB_16MB_SIZE 0x01000000
	79	#define TLB_1MB_SIZE 0x00100000
	80	#define TLB_256KB_SIZE 0x00040000
	81	#define TLB_64KB_SIZE 0x00010000
	82	#define TLB_16KB_SIZE 0x00004000
	83	#define TLB_4KB_SIZE 0x00001000
	84	#define TLB_1KB_SIZE 0x00000400
	85
	86	#define TLB_WORD0_EPN_MASK 0xFFFFFC00
	87	#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
	88	#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
	89	#define TLB_WORD0_V_MASK 0x00000200
	90	#define TLB_WORD0_V_ENABLE 0x00000200
	91	#define TLB_WORD0_V_DISABLE 0x00000000
	92	#define TLB_WORD0_TS_MASK 0x00000100
	93	#define TLB_WORD0_TS_1 0x00000100
	94	#define TLB_WORD0_TS_0 0x00000000
	95	#define TLB_WORD0_SIZE_MASK 0x000000F0
	96	#define TLB_WORD0_SIZE_1KB 0x00000000
	97	#define TLB_WORD0_SIZE_4KB 0x00000010
	98	#define TLB_WORD0_SIZE_16KB 0x00000020
	99	#define TLB_WORD0_SIZE_64KB 0x00000030
	100	#define TLB_WORD0_SIZE_256KB 0x00000040
	101	#define TLB_WORD0_SIZE_1MB 0x00000050
	102	#define TLB_WORD0_SIZE_16MB 0x00000070
	103	#define TLB_WORD0_SIZE_256MB 0x00000090
	104	#define TLB_WORD0_TPAR_MASK 0x0000000F
	105	#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
	106	#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
	107
	108	#define TLB_WORD1_RPN_MASK 0xFFFFFC00
	109	#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
	110	#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
	111	#define TLB_WORD1_PAR1_MASK 0x00000300
	112	#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
	113	#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
	114	#define TLB_WORD1_PAR1_0 0x00000000
	115	#define TLB_WORD1_PAR1_1 0x00000100
	116	#define TLB_WORD1_PAR1_2 0x00000200
	117	#define TLB_WORD1_PAR1_3 0x00000300
	118	#define TLB_WORD1_ERPN_MASK 0x0000000F
	119	#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
	120	#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
	121
	122	#define TLB_WORD2_PAR2_MASK 0xC0000000
	123	#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
	124	#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
	125	#define TLB_WORD2_PAR2_0 0x00000000
	126	#define TLB_WORD2_PAR2_1 0x40000000
	127	#define TLB_WORD2_PAR2_2 0x80000000
	128	#define TLB_WORD2_PAR2_3 0xC0000000
	129	#define TLB_WORD2_U0_MASK 0x00008000
130	#define TLB_WORD2_U0_ENABLE 0x00008000
131	#define TLB_WORD2_U0_DISABLE 0x00000000
132	#define TLB_WORD2_U1_MASK 0x00004000
133	#define TLB_WORD2_U1_ENABLE 0x00004000
134	#define TLB_WORD2_U1_DISABLE 0x00000000
135	#define TLB_WORD2_U2_MASK 0x00002000
136	#define TLB_WORD2_U2_ENABLE 0x00002000
137	#define TLB_WORD2_U2_DISABLE 0x00000000
138	#define TLB_WORD2_U3_MASK 0x00001000
139	#define TLB_WORD2_U3_ENABLE 0x00001000
140	#define TLB_WORD2_U3_DISABLE 0x00000000
141	#define TLB_WORD2_W_MASK 0x00000800
142	#define TLB_WORD2_W_ENABLE 0x00000800
143	#define TLB_WORD2_W_DISABLE 0x00000000
144	#define TLB_WORD2_I_MASK 0x00000400
145	#define TLB_WORD2_I_ENABLE 0x00000400
146	#define TLB_WORD2_I_DISABLE 0x00000000
147	#define TLB_WORD2_M_MASK 0x00000200
148	#define TLB_WORD2_M_ENABLE 0x00000200
149	#define TLB_WORD2_M_DISABLE 0x00000000
150	#define TLB_WORD2_G_MASK 0x00000100
151	#define TLB_WORD2_G_ENABLE 0x00000100
152	#define TLB_WORD2_G_DISABLE 0x00000000
153	#define TLB_WORD2_E_MASK 0x00000080
154	#define TLB_WORD2_E_ENABLE 0x00000080
155	#define TLB_WORD2_E_DISABLE 0x00000000
156	#define TLB_WORD2_UX_MASK 0x00000020
157	#define TLB_WORD2_UX_ENABLE 0x00000020
158	#define TLB_WORD2_UX_DISABLE 0x00000000
159	#define TLB_WORD2_UW_MASK 0x00000010
160	#define TLB_WORD2_UW_ENABLE 0x00000010
161	#define TLB_WORD2_UW_DISABLE 0x00000000
162	#define TLB_WORD2_UR_MASK 0x00000008
163	#define TLB_WORD2_UR_ENABLE 0x00000008
164	#define TLB_WORD2_UR_DISABLE 0x00000000
165	#define TLB_WORD2_SX_MASK 0x00000004
166	#define TLB_WORD2_SX_ENABLE 0x00000004
167	#define TLB_WORD2_SX_DISABLE 0x00000000
168	#define TLB_WORD2_SW_MASK 0x00000002
169	#define TLB_WORD2_SW_ENABLE 0x00000002
170	#define TLB_WORD2_SW_DISABLE 0x00000000
171	#define TLB_WORD2_SR_MASK 0x00000001
172	#define TLB_WORD2_SR_ENABLE 0x00000001
173	#define TLB_WORD2_SR_DISABLE 0x00000000
174
175	/*----------------------------------------------------------------------------+
176	\| Board specific defines.
177	+----------------------------------------------------------------------------*/
178	#define NONCACHE_MEMORY_SIZE (64*1024)
179	#define NONCACHE_AREA0_ENDOFFSET (64*1024)
180	#define NONCACHE_AREA1_ENDOFFSET (32*1024)
181
182	#define FLASH_SECTORSIZE 0x00010000
183
184	/* SDRAM MICRON */
185	#define SDRAM_MICRON 0x2C
186
187	#define SDRAM_TRUE 1
188	#define SDRAM_FALSE 0
189	#define SDRAM_DDR1 1
190	#define SDRAM_DDR2 2
191	#define SDRAM_NONE 0
192	#define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */
193	#define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */
194	#define MAXBANKSPERDIMM 2
195	#define MAXRANKSPERDIMM 2
196	#define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */
197	#define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */
198	#define ERROR_STR_LENGTH 256
199	#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
200
201	/*----------------------------------------------------------------------------+
202	\| SDR Configuration registers
203	+----------------------------------------------------------------------------*/
204	/* Serial Device Strap Reg 0 */
205	#define sdr_pstrp0 0x0040
206
207	#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */
208	#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */
209	#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
210
211	#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */
212	#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
213	#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */
214
215	#define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */
216	#define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */
217	#define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */
218	#define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */
219	#define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */
220
221	/* Serial Device Enabled - Addr = 0xA8 */
222	#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
223	/* Serial Device Enabled - Addr = 0xA4 */
224	#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
225
226	/* Pin Straps Reg */
227	#define SDR0_PSTRP0 0x0040
228	#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
229
230	#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
231	#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
232	#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
233	#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
234	#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
235	#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
236	#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
237	#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
238
239	/* fpgareg - defines are in include/config/YUCCA.h */
240
241	#define SDR0_CUST0_ENET3_MASK 0x00000080
242	#define SDR0_CUST0_ENET3_COPPER 0x00000000
243	#define SDR0_CUST0_ENET3_FIBER 0x00000080
244	#define SDR0_CUST0_RGMII3_MASK 0x00000070
245	#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
246	#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
247	#define SDR0_CUST0_RGMII3_DISAB 0x00000000
248	#define SDR0_CUST0_RGMII3_RTBI 0x00000040
249	#define SDR0_CUST0_RGMII3_RGMII 0x00000050
250	#define SDR0_CUST0_RGMII3_TBI 0x00000060
251	#define SDR0_CUST0_RGMII3_GMII 0x00000070
252	#define SDR0_CUST0_ENET2_MASK 0x00000008
253	#define SDR0_CUST0_ENET2_COPPER 0x00000000
254	#define SDR0_CUST0_ENET2_FIBER 0x00000008
255	#define SDR0_CUST0_RGMII2_MASK 0x00000007
256	#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
257	#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
258	#define SDR0_CUST0_RGMII2_DISAB 0x00000000
259	#define SDR0_CUST0_RGMII2_RTBI 0x00000004
260	#define SDR0_CUST0_RGMII2_RGMII 0x00000005
261	#define SDR0_CUST0_RGMII2_TBI 0x00000006
262	#define SDR0_CUST0_RGMII2_GMII 0x00000007
263
264	#define ONE_MILLION 1000000
265	#define ONE_BILLION 1000000000
266
267	/*----------------------------------------------------------------------------+
268	\| X
269	\| XX
270	\| XX XXX XXXXX XX XXX XXXXX
271	\| XX XX X XXX XX XX
272	\| XX XX XXXXXX XX XX
273	\| XX XX X XX XX XX XX
274	\| XXX XX XXXXX X XXXX XXX
275	+----------------------------------------------------------------------------*/
276	/*----------------------------------------------------------------------------+
277	\| Declare Configuration values
278	+----------------------------------------------------------------------------*/
279
280	typedef enum config_selection {
281	CONFIG_NOT_SELECTED,
282	CONFIG_SELECTED
283	} config_selection_t;
284
285	typedef enum config_list {
286	UART2_IN_SERVICE_MODE,
287	CPU_TRACE_MODE,
288	UART1_CTS_RTS,
289	CONFIG_NB
290	} config_list_t;
291
292	#define MAX_CONFIG_SELECT_NB 3
293
294	#define BOARD_INFO_UART2_IN_SERVICE_MODE 1
295	#define BOARD_INFO_CPU_TRACE_MODE 2
296	#define BOARD_INFO_UART1_CTS_RTS_MODE 4
297
298	void force_bup_config_selection(config_selection_t *confgi_select_P);
299	void update_config_selection_table(config_selection_t *config_select_P);
300	void display_config_selection(config_selection_t *config_select_P);
301
302	/*----------------------------------------------------------------------------+
303	\| XX
304	\|
305	\| XXXX XX XXX XXX XXXX
306	\| XX XX XX XX XX XX
307	\| XX XXX XX XX XX XX XX
308	\| XX XX XXXXX XX XX XX
309	\| XXXX XX XXXX XXXX
310	\| XXXX
311	\|
312	\|
313	\|
314	\| +------------------------------------------------------------------+
315	\| \| GPIO/Secondary func \| Primary Function \| I/O \| Alternate1 \| I/O \|
316	\| +----------------------+------------------+-----+------------+-----+
317	\| \| \| \| \| \| \|
318	\| \| GPIO0_0 \| PCIX0REQ2_N \| I/O \| TRCCLK \| \|
319	\| \| GPIO0_1 \| PCIX0REQ3_N \| I/O \| TRCBS0 \| \|
320	\| \| GPIO0_2 \| PCIX0GNT2_N \| I/O \| TRCBS1 \| \|
321	\| \| GPIO0_3 \| PCIX0GNT3_N \| I/O \| TRCBS2 \| \|
322	\| \| GPIO0_4 \| PCIX1REQ2_N \| I/O \| TRCES0 \| \|
323	\| \| GPIO0_5 \| PCIX1REQ3_N \| I/O \| TRCES1 \| \|
324	\| \| GPIO0_6 \| PCIX1GNT2_N \| I/O \| TRCES2 \| NA \|
325	\| \| GPIO0_7 \| PCIX1GNT3_N \| I/O \| TRCES3 \| NA \|
326	\| \| GPIO0_8 \| PERREADY \| I \| TRCES4 \| NA \|
327	\| \| GPIO0_9 \| PERCS1_N \| O \| TRCTS0 \| NA \|
328	\| \| GPIO0_10 \| PERCS2_N \| O \| TRCTS1 \| NA \|
329	\| \| GPIO0_11 \| IRQ0 \| I \| TRCTS2 \| NA \|
330	\| \| GPIO0_12 \| IRQ1 \| I \| TRCTS3 \| NA \|
331	\| \| GPIO0_13 \| IRQ2 \| I \| TRCTS4 \| NA \|
332	\| \| GPIO0_14 \| IRQ3 \| I \| TRCTS5 \| NA \|
333	\| \| GPIO0_15 \| IRQ4 \| I \| TRCTS6 \| NA \|
334	\| \| GPIO0_16 \| IRQ5 \| I \| UART2RX \| I \|
335	\| \| GPIO0_17 \| PERBE0_N \| O \| UART2TX \| O \|
336	\| \| GPIO0_18 \| PCI0GNT0_N \| I/O \| NA \| NA \|
337	\| \| GPIO0_19 \| PCI0GNT1_N \| I/O \| NA \| NA \|
338	\| \| GPIO0_20 \| PCI0REQ0_N \| I/O \| NA \| NA \|
339	\| \| GPIO0_21 \| PCI0REQ1_N \| I/O \| NA \| NA \|
340	\| \| GPIO0_22 \| PCI1GNT0_N \| I/O \| NA \| NA \|
341	\| \| GPIO0_23 \| PCI1GNT1_N \| I/O \| NA \| NA \|
342	\| \| GPIO0_24 \| PCI1REQ0_N \| I/O \| NA \| NA \|
343	\| \| GPIO0_25 \| PCI1REQ1_N \| I/O \| NA \| NA \|
344	\| \| GPIO0_26 \| PCI2GNT0_N \| I/O \| NA \| NA \|
345	\| \| GPIO0_27 \| PCI2GNT1_N \| I/O \| NA \| NA \|
346	\| \| GPIO0_28 \| PCI2REQ0_N \| I/O \| NA \| NA \|
347	\| \| GPIO0_29 \| PCI2REQ1_N \| I/O \| NA \| NA \|
348	\| \| GPIO0_30 \| UART1RX \| I \| NA \| NA \|
349	\| \| GPIO0_31 \| UART1TX \| O \| NA \| NA \|
350	\| \| \| \| \| \| \|
351	\| +----------------------+------------------+-----+------------+-----+
352	\|
353	+----------------------------------------------------------------------------*/
354
6c5879f3 MB	355	unsigned long auto_calc_speed(void);
	356	/*----------------------------------------------------------------------------+
	357	\| Prototypes
	358	+----------------------------------------------------------------------------*/
	359	void print_evb440spe_info(void);
	360
	361	int onboard_pci_arbiter_selected(int core_pci);
	362
	363	#ifdef __cplusplus
	364	}
	365	#endif
	366	#endif /* __YUCCA_H_ */