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7254d92e HS |
1 | /* |
2 | * (C) Copyright 2015 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
5 | * Based on: | |
6 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
7 | * | |
8 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #include <asm/arch/clock.h> | |
14 | #include <asm/arch/imx-regs.h> | |
15 | #include <asm/arch/iomux.h> | |
16 | #include <asm/arch/mx6-pins.h> | |
1221ce45 | 17 | #include <linux/errno.h> |
7254d92e | 18 | #include <asm/gpio.h> |
552a848e SB |
19 | #include <asm/mach-imx/iomux-v3.h> |
20 | #include <asm/mach-imx/boot_mode.h> | |
21 | #include <asm/mach-imx/mxc_i2c.h> | |
22 | #include <asm/mach-imx/video.h> | |
7254d92e HS |
23 | #include <mmc.h> |
24 | #include <fsl_esdhc.h> | |
25 | #include <miiphy.h> | |
26 | #include <netdev.h> | |
27 | #include <asm/arch/mxc_hdmi.h> | |
28 | #include <asm/arch/crm_regs.h> | |
29 | #include <linux/fb.h> | |
30 | #include <ipu_pixfmt.h> | |
31 | #include <asm/io.h> | |
32 | #include <asm/arch/sys_proto.h> | |
33 | #include <pwm.h> | |
34 | #include <micrel.h> | |
35 | #include <spi.h> | |
36 | #include <video.h> | |
37 | #include <../drivers/video/ipu.h> | |
38 | #if defined(CONFIG_VIDEO_BMP_LOGO) | |
39 | #include <bmp_logo.h> | |
40 | #endif | |
41 | ||
42 | #define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \ | |
43 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | |
44 | ||
9627084c HS |
45 | #if (CONFIG_SYS_BOARD_VERSION == 2) |
46 | /* 4.3 display controller */ | |
47 | #define ECSPI1_CS0 IMX_GPIO_NR(4, 9) | |
48 | #define ECSPI4_CS0 IMX_GPIO_NR(3, 29) | |
49 | #elif (CONFIG_SYS_BOARD_VERSION == 3) | |
50 | #define ECSPI1_CS0 IMX_GPIO_NR(2, 30) /* NOR flash */ | |
51 | /* 4.3 display controller */ | |
52 | #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) | |
53 | #endif | |
54 | ||
7254d92e HS |
55 | #define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13) |
56 | #define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8) | |
57 | ||
58 | struct i2c_pads_info i2c_pad_info3 = { | |
59 | .scl = { | |
60 | .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, | |
61 | .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, | |
62 | .gp = IMX_GPIO_NR(1, 5) | |
63 | }, | |
64 | .sda = { | |
65 | .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, | |
66 | .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, | |
67 | .gp = IMX_GPIO_NR(1, 6) | |
68 | } | |
69 | }; | |
70 | ||
71 | struct i2c_pads_info i2c_pad_info4 = { | |
72 | .scl = { | |
73 | .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC, | |
74 | .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC, | |
75 | .gp = IMX_GPIO_NR(1, 7) | |
76 | }, | |
77 | .sda = { | |
78 | .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC, | |
79 | .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC, | |
80 | .gp = IMX_GPIO_NR(1, 8) | |
81 | } | |
82 | }; | |
83 | ||
84 | iomux_v3_cfg_t const uart1_pads[] = { | |
85 | MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
86 | MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
87 | MX6_PAD_EIM_D19__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
88 | MX6_PAD_EIM_D20__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
89 | }; | |
90 | ||
91 | iomux_v3_cfg_t const uart2_pads[] = { | |
92 | MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
93 | MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
94 | }; | |
95 | ||
96 | iomux_v3_cfg_t const uart3_pads[] = { | |
97 | MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
98 | MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
99 | MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
100 | MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
101 | }; | |
102 | ||
103 | iomux_v3_cfg_t const uart4_pads[] = { | |
104 | MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
105 | MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
106 | }; | |
107 | ||
108 | iomux_v3_cfg_t const gpio_pads[] = { | |
109 | /* LED enable*/ | |
110 | MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
111 | /* LED yellow */ | |
112 | MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
113 | /* LED red */ | |
9627084c | 114 | #if (CONFIG_SYS_BOARD_VERSION == 2) |
7254d92e | 115 | MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), |
9627084c HS |
116 | #elif (CONFIG_SYS_BOARD_VERSION == 3) |
117 | MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
118 | #endif | |
7254d92e HS |
119 | /* LED green */ |
120 | MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
121 | /* LED blue */ | |
122 | MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
123 | /* spi flash WP protect */ | |
124 | MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
125 | /* spi CS 0 */ | |
126 | MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
127 | /* spi bus #2 SS driver enable */ | |
128 | MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
129 | /* RST_LOC# PHY reset input (has pull-down!)*/ | |
130 | MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
131 | /* SD 2 level shifter output enable */ | |
132 | MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
133 | /* SD1 card detect input */ | |
134 | MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
135 | /* SD1 write protect input */ | |
136 | MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
137 | /* SD2 card detect input */ | |
138 | MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
139 | /* SD2 write protect input */ | |
140 | MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
141 | /* Touchscreen IRQ */ | |
142 | MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
143 | }; | |
144 | ||
145 | static iomux_v3_cfg_t const misc_pads[] = { | |
146 | /* USB_OTG_ID = GPIO1_24*/ | |
147 | MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), | |
148 | /* H1 Power enable = GPIO1_0*/ | |
149 | MX6_PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), | |
150 | /* OTG Power enable = GPIO4_15*/ | |
151 | MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), | |
152 | }; | |
153 | ||
154 | iomux_v3_cfg_t const enet_pads[] = { | |
155 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
156 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
157 | MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
158 | MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
159 | MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
160 | MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
161 | MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
162 | MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
163 | MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
164 | MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
165 | MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
166 | MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
167 | MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
168 | MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
169 | MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
170 | }; | |
171 | ||
172 | static iomux_v3_cfg_t const backlight_pads[] = { | |
173 | /* backlight PWM brightness control */ | |
174 | MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), | |
175 | /* backlight enable */ | |
176 | MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
177 | /* LCD power enable */ | |
178 | MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
179 | }; | |
180 | ||
181 | static iomux_v3_cfg_t const ecspi1_pads[] = { | |
182 | MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
183 | MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
184 | MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
9627084c | 185 | #if (CONFIG_SYS_BOARD_VERSION == 2) |
7254d92e | 186 | MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL), |
9627084c HS |
187 | #elif (CONFIG_SYS_BOARD_VERSION == 3) |
188 | MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
189 | MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
190 | #endif | |
7254d92e HS |
191 | }; |
192 | ||
193 | static void setup_iomux_enet(void) | |
194 | { | |
195 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); | |
196 | } | |
197 | ||
9627084c | 198 | #if (CONFIG_SYS_BOARD_VERSION == 2) |
7254d92e HS |
199 | iomux_v3_cfg_t const ecspi4_pads[] = { |
200 | MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL), | |
201 | MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL), | |
202 | MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL), | |
203 | MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
204 | MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
205 | }; | |
9627084c | 206 | #endif |
7254d92e HS |
207 | |
208 | static iomux_v3_cfg_t const display_pads[] = { | |
209 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), | |
210 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, | |
211 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, | |
212 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, | |
7254d92e HS |
213 | MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, |
214 | MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, | |
215 | MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, | |
216 | MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, | |
217 | MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, | |
218 | MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, | |
219 | MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, | |
220 | MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, | |
221 | MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, | |
222 | MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, | |
223 | MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, | |
224 | MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, | |
225 | MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, | |
226 | MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, | |
227 | MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, | |
228 | MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, | |
229 | MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, | |
230 | MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, | |
231 | MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, | |
232 | MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, | |
233 | MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, | |
234 | MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, | |
235 | MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, | |
236 | MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, | |
237 | }; | |
238 | ||
239 | int board_spi_cs_gpio(unsigned bus, unsigned cs) | |
240 | { | |
241 | if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) | |
9627084c | 242 | #if (CONFIG_SYS_BOARD_VERSION == 2) |
7254d92e HS |
243 | return IMX_GPIO_NR(5, 2); |
244 | ||
245 | if (bus == 0 && cs == 0) | |
246 | return IMX_GPIO_NR(4, 9); | |
9627084c HS |
247 | #elif (CONFIG_SYS_BOARD_VERSION == 3) |
248 | return ECSPI1_CS0; | |
7254d92e | 249 | |
9627084c HS |
250 | if (bus == 0 && cs == 1) |
251 | return ECSPI1_CS1; | |
252 | #endif | |
7254d92e HS |
253 | return -1; |
254 | } | |
255 | ||
256 | static void setup_spi(void) | |
257 | { | |
258 | int i; | |
259 | ||
260 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); | |
9627084c HS |
261 | |
262 | #if (CONFIG_SYS_BOARD_VERSION == 2) | |
7254d92e | 263 | imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); |
9627084c HS |
264 | #endif |
265 | ||
7254d92e HS |
266 | for (i = 0; i < 4; i++) |
267 | enable_spi_clk(true, i); | |
268 | ||
269 | gpio_direction_output(ECSPI1_CS0, 1); | |
9627084c | 270 | #if (CONFIG_SYS_BOARD_VERSION == 2) |
7254d92e | 271 | gpio_direction_output(ECSPI4_CS1, 0); |
7254d92e HS |
272 | /* set cs0 to high (second device on spi bus #4) */ |
273 | gpio_direction_output(ECSPI4_CS0, 1); | |
9627084c HS |
274 | #elif (CONFIG_SYS_BOARD_VERSION == 3) |
275 | gpio_direction_output(ECSPI1_CS1, 1); | |
276 | #endif | |
7254d92e HS |
277 | } |
278 | ||
279 | static void setup_iomux_uart(void) | |
280 | { | |
281 | switch (CONFIG_MXC_UART_BASE) { | |
282 | case UART1_BASE: | |
283 | imx_iomux_v3_setup_multiple_pads(uart1_pads, | |
284 | ARRAY_SIZE(uart1_pads)); | |
285 | break; | |
286 | case UART2_BASE: | |
287 | imx_iomux_v3_setup_multiple_pads(uart2_pads, | |
288 | ARRAY_SIZE(uart2_pads)); | |
289 | break; | |
290 | case UART3_BASE: | |
291 | imx_iomux_v3_setup_multiple_pads(uart3_pads, | |
292 | ARRAY_SIZE(uart3_pads)); | |
293 | break; | |
294 | case UART4_BASE: | |
295 | imx_iomux_v3_setup_multiple_pads(uart4_pads, | |
296 | ARRAY_SIZE(uart4_pads)); | |
297 | break; | |
298 | } | |
299 | } | |
300 | ||
301 | int board_phy_config(struct phy_device *phydev) | |
302 | { | |
303 | /* control data pad skew - devaddr = 0x02, register = 0x04 */ | |
304 | ksz9031_phy_extended_write(phydev, 0x02, | |
305 | MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, | |
306 | MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); | |
307 | /* rx data pad skew - devaddr = 0x02, register = 0x05 */ | |
308 | ksz9031_phy_extended_write(phydev, 0x02, | |
309 | MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, | |
310 | MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); | |
311 | /* tx data pad skew - devaddr = 0x02, register = 0x06 */ | |
312 | ksz9031_phy_extended_write(phydev, 0x02, | |
313 | MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, | |
314 | MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); | |
315 | /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ | |
316 | ksz9031_phy_extended_write(phydev, 0x02, | |
317 | MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, | |
318 | MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); | |
319 | ||
320 | if (phydev->drv->config) | |
321 | phydev->drv->config(phydev); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | int board_eth_init(bd_t *bis) | |
327 | { | |
328 | setup_iomux_enet(); | |
329 | return cpu_eth_init(bis); | |
330 | } | |
331 | ||
332 | static int rotate_logo_one(unsigned char *out, unsigned char *in) | |
333 | { | |
334 | int i, j; | |
335 | ||
336 | for (i = 0; i < BMP_LOGO_WIDTH; i++) | |
337 | for (j = 0; j < BMP_LOGO_HEIGHT; j++) | |
338 | out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] = | |
339 | in[i * BMP_LOGO_WIDTH + j]; | |
340 | return 0; | |
341 | } | |
342 | ||
343 | /* | |
344 | * Rotate the BMP_LOGO (only) | |
345 | * Will only work, if the logo is square, as | |
346 | * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables | |
347 | */ | |
348 | void rotate_logo(int rotations) | |
349 | { | |
350 | unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT]; | |
351 | unsigned char *in_logo; | |
352 | int i, j; | |
353 | ||
354 | if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT) | |
355 | return; | |
356 | ||
357 | in_logo = bmp_logo_bitmap; | |
358 | ||
359 | /* one 90 degree rotation */ | |
360 | if (rotations == 1 || rotations == 2 || rotations == 3) | |
361 | rotate_logo_one(out_logo, in_logo); | |
362 | ||
363 | /* second 90 degree rotation */ | |
364 | if (rotations == 2 || rotations == 3) | |
365 | rotate_logo_one(in_logo, out_logo); | |
366 | ||
367 | /* third 90 degree rotation */ | |
368 | if (rotations == 3) | |
369 | rotate_logo_one(out_logo, in_logo); | |
370 | ||
371 | /* copy result back to original array */ | |
372 | if (rotations == 1 || rotations == 3) | |
373 | for (i = 0; i < BMP_LOGO_WIDTH; i++) | |
374 | for (j = 0; j < BMP_LOGO_HEIGHT; j++) | |
375 | in_logo[i * BMP_LOGO_WIDTH + j] = | |
376 | out_logo[i * BMP_LOGO_WIDTH + j]; | |
377 | } | |
378 | ||
379 | static void enable_display_power(void) | |
380 | { | |
381 | imx_iomux_v3_setup_multiple_pads(backlight_pads, | |
382 | ARRAY_SIZE(backlight_pads)); | |
383 | ||
384 | /* backlight enable */ | |
385 | gpio_direction_output(IMX_GPIO_NR(6, 31), 1); | |
386 | /* LCD power enable */ | |
387 | gpio_direction_output(IMX_GPIO_NR(6, 15), 1); | |
388 | ||
389 | /* enable backlight PWM 1 */ | |
390 | if (pwm_init(0, 0, 0)) | |
391 | goto error; | |
392 | /* duty cycle 500ns, period: 3000ns */ | |
393 | if (pwm_config(0, 50000, 300000)) | |
394 | goto error; | |
395 | if (pwm_enable(0)) | |
396 | goto error; | |
397 | return; | |
398 | ||
399 | error: | |
400 | puts("error init pwm for backlight\n"); | |
401 | return; | |
402 | } | |
403 | ||
404 | static void enable_lvds(struct display_info_t const *dev) | |
405 | { | |
406 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
407 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
408 | int reg; | |
409 | s32 timeout = 100000; | |
410 | ||
411 | /* set PLL5 clock */ | |
412 | reg = readl(&ccm->analog_pll_video); | |
413 | reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; | |
414 | writel(reg, &ccm->analog_pll_video); | |
415 | ||
416 | /* set PLL5 to 232720000Hz */ | |
417 | reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; | |
418 | reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26); | |
419 | reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; | |
420 | reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); | |
421 | writel(reg, &ccm->analog_pll_video); | |
422 | ||
423 | writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238), | |
424 | &ccm->analog_pll_video_num); | |
425 | writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240), | |
426 | &ccm->analog_pll_video_denom); | |
427 | ||
428 | reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; | |
429 | writel(reg, &ccm->analog_pll_video); | |
430 | ||
431 | while (timeout--) | |
432 | if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) | |
433 | break; | |
434 | if (timeout < 0) | |
435 | printf("Warning: video pll lock timeout!\n"); | |
436 | ||
437 | reg = readl(&ccm->analog_pll_video); | |
438 | reg |= BM_ANADIG_PLL_VIDEO_ENABLE; | |
439 | reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; | |
440 | writel(reg, &ccm->analog_pll_video); | |
441 | ||
442 | /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ | |
443 | reg = readl(&ccm->cs2cdr); | |
444 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | |
445 | | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); | |
446 | reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | |
447 | | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); | |
448 | writel(reg, &ccm->cs2cdr); | |
449 | ||
450 | reg = readl(&ccm->cscmr2); | |
451 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; | |
452 | writel(reg, &ccm->cscmr2); | |
453 | ||
454 | reg = readl(&ccm->chsccdr); | |
455 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 | |
456 | << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); | |
457 | writel(reg, &ccm->chsccdr); | |
458 | ||
459 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | |
460 | | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | |
461 | | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH | |
462 | | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | |
463 | | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | |
464 | | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | |
465 | | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; | |
466 | writel(reg, &iomux->gpr[2]); | |
467 | ||
468 | reg = readl(&iomux->gpr[3]); | |
469 | reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | |
470 | | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 | |
471 | << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); | |
472 | writel(reg, &iomux->gpr[3]); | |
473 | ||
474 | return; | |
475 | } | |
476 | ||
477 | static void enable_spi_display(struct display_info_t const *dev) | |
478 | { | |
479 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
480 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
481 | int reg; | |
482 | s32 timeout = 100000; | |
483 | ||
484 | #if defined(CONFIG_VIDEO_BMP_LOGO) | |
485 | rotate_logo(3); /* portrait display in landscape mode */ | |
486 | #endif | |
487 | ||
488 | /* | |
489 | * set ldb clock to 28341000 Hz calculated through the formula: | |
490 | * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) * | |
491 | * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH) | |
492 | * see: | |
493 | * https://community.freescale.com/thread/308170 | |
494 | */ | |
495 | ipu_set_ldb_clock(28341000); | |
496 | ||
497 | reg = readl(&ccm->cs2cdr); | |
498 | ||
499 | /* select pll 5 clock */ | |
500 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | |
501 | | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); | |
502 | writel(reg, &ccm->cs2cdr); | |
503 | ||
504 | /* set PLL5 to 197994996Hz */ | |
505 | reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; | |
506 | reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21); | |
507 | reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; | |
508 | reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); | |
509 | writel(reg, &ccm->analog_pll_video); | |
510 | ||
511 | writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4), | |
512 | &ccm->analog_pll_video_num); | |
513 | writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240), | |
514 | &ccm->analog_pll_video_denom); | |
515 | ||
516 | reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; | |
517 | writel(reg, &ccm->analog_pll_video); | |
518 | ||
519 | while (timeout--) | |
520 | if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) | |
521 | break; | |
522 | if (timeout < 0) | |
523 | printf("Warning: video pll lock timeout!\n"); | |
524 | ||
525 | reg = readl(&ccm->analog_pll_video); | |
526 | reg |= BM_ANADIG_PLL_VIDEO_ENABLE; | |
527 | reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; | |
528 | writel(reg, &ccm->analog_pll_video); | |
529 | ||
530 | /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ | |
531 | reg = readl(&ccm->cs2cdr); | |
532 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | |
533 | | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); | |
534 | reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | |
535 | | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); | |
536 | writel(reg, &ccm->cs2cdr); | |
537 | ||
538 | reg = readl(&ccm->cscmr2); | |
539 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; | |
540 | writel(reg, &ccm->cscmr2); | |
541 | ||
542 | reg = readl(&ccm->chsccdr); | |
543 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 | |
544 | << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); | |
545 | reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; | |
546 | reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET); | |
547 | reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; | |
548 | reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); | |
549 | writel(reg, &ccm->chsccdr); | |
550 | ||
551 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | |
552 | | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | |
553 | | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH | |
554 | | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | |
555 | | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | |
556 | | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | |
557 | | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; | |
558 | writel(reg, &iomux->gpr[2]); | |
559 | ||
560 | reg = readl(&iomux->gpr[3]); | |
561 | reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | |
562 | | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 | |
563 | << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); | |
564 | writel(reg, &iomux->gpr[3]); | |
565 | ||
566 | imx_iomux_v3_setup_multiple_pads( | |
567 | display_pads, | |
568 | ARRAY_SIZE(display_pads)); | |
569 | ||
570 | return; | |
571 | } | |
572 | static void setup_display(void) | |
573 | { | |
574 | enable_ipu_clock(); | |
575 | enable_display_power(); | |
576 | } | |
577 | ||
578 | static void setup_iomux_gpio(void) | |
579 | { | |
580 | imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); | |
581 | } | |
582 | ||
c39fcad7 HS |
583 | static void set_gpr_register(void) |
584 | { | |
585 | struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
586 | ||
587 | writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 | | |
588 | IOMUXC_GPR1_EXC_MON_SLVE | | |
589 | (2 << IOMUXC_GPR1_ADDRS0_OFFSET) | | |
590 | IOMUXC_GPR1_ACT_CS0, | |
591 | &iomuxc_regs->gpr[1]); | |
592 | writel(0x0, &iomuxc_regs->gpr[8]); | |
593 | writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN | | |
594 | IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN, | |
595 | &iomuxc_regs->gpr[12]); | |
596 | } | |
597 | ||
7254d92e HS |
598 | int board_early_init_f(void) |
599 | { | |
600 | setup_iomux_uart(); | |
601 | setup_iomux_gpio(); | |
602 | ||
603 | gpio_direction_output(SOFT_RESET_GPIO, 1); | |
604 | gpio_direction_output(SD2_DRIVER_ENABLE, 1); | |
605 | setup_display(); | |
c39fcad7 | 606 | set_gpr_register(); |
7254d92e HS |
607 | return 0; |
608 | } | |
609 | ||
610 | static void setup_i2c4(void) | |
611 | { | |
612 | setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, | |
613 | &i2c_pad_info4); | |
614 | } | |
615 | ||
616 | static void setup_board_gpio(void) | |
617 | { | |
618 | /* enable all LEDs */ | |
619 | gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */ | |
620 | gpio_direction_output(IMX_GPIO_NR(1, 25), 0); | |
621 | ||
622 | /* switch off Status LEDs */ | |
9627084c | 623 | #if (CONFIG_SYS_BOARD_VERSION == 2) |
7254d92e HS |
624 | gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ |
625 | gpio_direction_output(IMX_GPIO_NR(6, 16), 1); | |
626 | gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */ | |
627 | gpio_direction_output(IMX_GPIO_NR(2, 28), 1); | |
628 | gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ | |
629 | gpio_direction_output(IMX_GPIO_NR(5, 4), 1); | |
630 | gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ | |
631 | gpio_direction_output(IMX_GPIO_NR(2, 29), 1); | |
9627084c HS |
632 | #elif (CONFIG_SYS_BOARD_VERSION == 3) |
633 | gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ | |
634 | gpio_direction_output(IMX_GPIO_NR(6, 16), 0); | |
635 | gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */ | |
636 | gpio_direction_output(IMX_GPIO_NR(5, 0), 0); | |
637 | gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ | |
638 | gpio_direction_output(IMX_GPIO_NR(5, 4), 0); | |
639 | gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ | |
640 | gpio_direction_output(IMX_GPIO_NR(2, 29), 0); | |
641 | #endif | |
7254d92e HS |
642 | } |
643 | ||
644 | static void setup_board_spi(void) | |
645 | { | |
9627084c | 646 | /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */ |
7254d92e HS |
647 | gpio_direction_output(IMX_GPIO_NR(6, 6), 1); |
648 | } | |
649 | ||
650 | int board_late_init(void) | |
651 | { | |
652 | char *my_bootdelay; | |
653 | char bootmode = 0; | |
00caae6d | 654 | char const *panel = env_get("panel"); |
7254d92e HS |
655 | |
656 | /* | |
657 | * Check the boot-source. If booting from NOR Flash, | |
658 | * disable bootdelay | |
659 | */ | |
660 | gpio_request(IMX_GPIO_NR(7, 6), "bootsel0"); | |
661 | gpio_direction_input(IMX_GPIO_NR(7, 6)); | |
662 | gpio_request(IMX_GPIO_NR(7, 7), "bootsel1"); | |
663 | gpio_direction_input(IMX_GPIO_NR(7, 7)); | |
664 | gpio_request(IMX_GPIO_NR(7, 1), "bootsel2"); | |
665 | gpio_direction_input(IMX_GPIO_NR(7, 1)); | |
666 | bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0; | |
667 | bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1; | |
668 | bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2; | |
669 | ||
670 | if (bootmode == 7) { | |
00caae6d | 671 | my_bootdelay = env_get("nor_bootdelay"); |
7254d92e | 672 | if (my_bootdelay != NULL) |
382bee57 | 673 | env_set("bootdelay", my_bootdelay); |
7254d92e | 674 | else |
382bee57 | 675 | env_set("bootdelay", "-2"); |
7254d92e HS |
676 | } |
677 | ||
678 | /* if we have the lg panel, we can initialze it now */ | |
679 | if (panel) | |
680 | if (!strcmp(panel, displays[1].mode.name)) | |
9627084c HS |
681 | lg4573_spi_startup(CONFIG_LG4573_BUS, |
682 | CONFIG_LG4573_CS, | |
683 | 10000000, SPI_MODE_0); | |
7254d92e HS |
684 | |
685 | return 0; | |
686 | } |